High bandwidth self-timed data clocking scheme for memory bus im

Details High bandwidth self-timed data clocking scheme for memory bus im High bandwidth self-timed data clocking scheme for memory bus im

1994-11-14

1996-08-27

Yusko, Donald J.

Communications: electrical

Continuously variable indicating

With meter reading

371 371, 371 53, 178 41C, 178 69H, 178 69L, H04L 116, H04Q 130, G06F 112

Patent

active

055505333

ABSTRACT:
A clocking scheme for transferring data between electronic devices. The clocking scheme includes sending a data request signal from a first device to a second device during a first system clocking period. The second device then sends the requested data and a corresponding data validation signal to the first device. The data validation signal latches the data into the second device. The data is latched by the validation signal in a time period that is typically shorter than the clocking period of the system clock.

REFERENCES:
patent: 4677433 (1987-06-01), Catlin et al.
patent: 5263172 (1993-11-01), Olnowich

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