High bandwidth reed-solomon encoding, decoding and error correct

Details High bandwidth reed-solomon encoding, decoding and error correct High bandwidth reed-solomon encoding, decoding and error correct

1990-01-25

1992-04-21

Baker, Stephen M.

Excavating

H03M 1300

Patent

active

051075032

ABSTRACT:
A pipelined error correction circuit iteratively determines syndromes, error locator and evaluator equations, and error locations and associated error values for received Reed-Solomon code words. The circuit includes a plurality of Galois Field multiplying circuits which use a minimum number of circiut elements to generate first and second products. Each Galois Field multiplying circuit includes a first GF multiplier which multiplies one of two input signals in each of two time intervals by a first value to produce a first product. The circuit includes a second GF multiplier which further multiplies one of the first products by a second value to generate a second product. The first and second products are then applied to the first GF multiplier as next input signals. The multiplying circuit minimizes the elements required to generate two products by using a first, relatively complex multiplier for both the first and second products and then a second relatively simple multiplier to generate the second product. This simplifies the multiplying circuit which would otherwise require two relatively complex multipliers. The error correction circuit determines, for each received code word, an error locator equation by iteratively updating a preliminary error locator equation. The circuit determines for a given iteration whether or not to update the preliminary error locator equation by comparing a particular variable with zero.

REFERENCES:
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patent: 4410989 (1983-10-01), Berlekamp
patent: 4649541 (1987-03-01), Lahmeyer
K. Y. Liu, "Architecture for VLSI Design of Reed-Solomon Decoders," IEEE Transactions on Computers, vol. C-33, No. 2, Feb. 1984, pp. 178-189.
R. E. Blahut, Theory and Practice of Error Control Codes, published by Addison-Wesley Publishing Co., Inc., May 1984, pp. 51-53, 79, 174, and 220-224.
Clark, Jr. et al., Error-Correction Coding for Digital Communications, Plenum Press, 1981, pp. 188-208.
H. M. Shao et al., "A VLSI Design of a Pipeline Reed-Salomon Decoder", IEEE Trans. on Computers, vol. C-34, No. 5, May 1985, pp. 393-403.

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