High bandwidth phase locked pool (PLL)

Details High bandwidth phase locked pool (PLL) High bandwidth phase locked pool (PLL)

2006-10-03

2008-09-23

Richards, N. Drew (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Synchronizing

C327S160000, C327S115000, C327S116000

Reexamination Certificate

active

07427883

ABSTRACT:
A phase locked loop (PLL) is provided. In one implementation, the PLL includes a feedback loop having a frequency multiplier and an integer divider to generate a divided signal. The PLL includes a re-sampling circuit operable to re-sample one or more digital pulses of the divided signal using one or more phase signals if a multiplication factor of the frequency multiplier does not divide evenly into the integer divisor.

REFERENCES:
patent: 6114882 (2000-09-01), Flynn
patent: 6114914 (2000-09-01), Mar
patent: 6525615 (2003-02-01), Masenas et al.
patent: 6542013 (2003-04-01), Volk et al.

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