Electricity: electrical systems and devices – Safety and protection of systems and devices – With specific voltage responsive fault sensor
Reexamination Certificate
2001-04-11
2003-09-16
Han, Jessica (Department: 2838)
Electricity: electrical systems and devices
Safety and protection of systems and devices
With specific voltage responsive fault sensor
C363S049000, C323S901000
Reexamination Certificate
active
06621675
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention is related to the field of voltage regulators, and particularly to a voltage regulator employed within a phase locked loop (PLL).
2. Description of the Related Art
Voltage regulators are used in a variety of systems to provide a regulated voltage to other circuits in the system. Generally, it is desirable to provide a stable regulated voltage in the face of a wide variety of loads, operating frequencies, etc.
A measure of the effectiveness of a voltage regulator is its power supply rejection ratio (PSRR), which measures the amount of noise present on the power supply to the voltage regulator which is transmitted to the regulated voltage. A high PSRR is indicative of a low amount of transmission of noise, and a low PSRR is indicative of a high amount of noise transmission. A high PSRR, particularly across a wide range of operating frequencies of the devices being supplied by the voltage regulator, is difficult to achieve.
For example, voltage regulators have been used in the past to power PLL circuitry. However, PSRRs of voltage regulators used in PLLs have been limited. For example, PSRRs greater than 25 dB may not been achieved in voltage regulators used in PLLS.
SUMMARY OF THE INVENTION
A voltage regulator is provided which may include one or more features for generating high PSRR. For example, source follower devices may be included in the voltage regulator for providing current sources for the output voltage nodes. The source followers may be sensitive to power supply noise at the gate terminal. Filters are included on the gate terminals to filter the power supply noise, thus reducing the noise at the gate terminals. As another example, the voltage regulator may employ current sources on the output voltage nodes which produce current inversely proportional to the current drawn by the load. Current variation on the output node may be reduced, which may ease the regulation of the voltage.
In one embodiment, the voltage regulator may include a power control circuit used to provide overvoltage protection during power up. For example, the above mentioned source followers may experience an overvoltage condition during power up since the gate terminals are charged through an RC time constant while the drain terminal may rapidly be powered to the power supply voltage. The power control circuit provides a voltage on the gate terminal during power up, and ceases providing the voltage after a time interval so that the circuit may operate.
While the above circuits are illustrated within a voltage regulator, they may also be used in other contexts, as desired.
Broadly speaking, a circuit is contemplated. The circuit includes a first N-type transistor having a first terminal coupled to a power supply, a second terminal and a first gate terminal. The circuit further includes a filter coupled between the power supply and the first gate terminal.
Additionally, a circuit is contemplated comprising a first transistor having a first terminal coupled to a power supply, a second terminal, and a first gate terminal; and a power control circuit. The power control circuit is configured, during a time period commencing at power up of the circuit, to supply a voltage to one of the second terminal and the first gate terminal to prevent an overvoltage condition on the first transistor. Additionally, the power control circuit is configured, at a termination of the time period, to cease supplying the voltage.
Moreover, a circuit is contemplated. The circuit includes an operational amplifier (op amp); a first transistor having a gate terminal coupled to an output of the op amp and having a first terminal and a second terminal; and a first current source. The first terminal is an output to which a load is couplable, the load being capable of drawing a variable current from the first terminal during operation. The first current source coupled to the first terminal and draws a first current from the first terminal which is inversely proportional to the current drawn by the load during operation.
REFERENCES:
patent: 3908159 (1975-09-01), Griffey
patent: 5130883 (1992-07-01), Edwards
patent: 5151665 (1992-09-01), Wentzler
patent: 5345119 (1994-09-01), Khoury
patent: 5404250 (1995-04-01), Hase et al.
patent: 5485126 (1996-01-01), Gersbach et al.
patent: 5512861 (1996-04-01), Sharma
patent: 5559474 (1996-09-01), Matsumoto et al.
patent: 5631587 (1997-05-01), Co et al.
patent: 5898336 (1999-04-01), Yamaguchi
patent: 5977806 (1999-11-01), Kikuchi
patent: 6037622 (2000-03-01), Lin et al.
patent: 6046626 (2000-04-01), Saeki et al.
patent: 6127880 (2000-10-01), Holst et al.
patent: 6320470 (2001-11-01), Arai et al.
patent: 6441660 (2002-08-01), Ingino, Jr.
patent: 6483358 (2002-11-01), Ingino, Jr.
patent: 282 673 (1988-09-01), None
Young, et al., “A PLL Clock Generator with 5 to 110 MHz of Lock Range for Microprocessors,” IEEE Journal of Slid-State Circuits, vol. 27, No. 11, Nov. 1992, 9 pages.
Vincent R. von Kaenel, “A High-Speed, Low-Power Clock Generator for a Microprocessor Application,” IEEE Journal of Solid-State Circuits, vol. 33, No. 11, Nov. 1998, 3 pages.
Patrik Larsson, Bell Labs, Lucent Technologies, Holmdel, NJ, “A2-1600NHz 1.2-2.5V CMOS Clock-Recovery PLL with Feedback Phase-Selection and Averaging Phase-Interpolation for Jitter Reduction,” IEEE International Solid-State Circuits Conference, ISSCC99/Session 20/Paper WA 20.6, 1999, 1 page.
Bult, et al., “A Fast-Settling CMOS Op Amp for SC Circuits with 90-dB DC Gain,” IEEE Journal of Solid-State Circuits, vol. 25, No. 6, Dec. 1990, 3 pages.
von Kaenel, et al., “A 320 MHz, 1.5 mW @ 1.35 V CMOS PLL for Microprocessor Clock Generation,” IEEE Journal of Solid-State Circuits, vol. 31, No. 11, Nov. 1996, 4 pages.
Horowitz, “The Art of Electronics,” Cambridge Univ. Press, 198015 pages.
SiByte, “Target Applications,” http://sibyte.com/mercurian/applications.htm, Jan. 15, 2001, 2 pages.
SiByte, “SiByte Technology,” http://sibyte.com/mercurian/technology.htm, Jan. 15, 2001, 3 pages.
SiByte, “The Mercurian Processor,” http://sibyte.com/mercurian, Jan. 15, 2001, 2 pages.
SiByte, “Fact Sheet,” SB-1 CPU, Oct. 2000, rev. 0.1, 1 page.
SiByte, “Fact Sheet,” SB-1250, Oct. 2000, rev. 0.2, 10 pages.
Stepanian, SiByte, SiByte SB-1 MIPS64 CPU Core, Embedded Processor Forum, 2000, Jun. 13, 2000, 15 pages.
Jim Keller, “The Mercurian Processor: A High Performance, Power-Efficient CMP for Networking,” Oct. 10, 2000, 22 pages.
Tom R. Halfhill, “SiByte Reveals 64-Bit Core For NPUs; Independent MIPS64 Design Combines Low Power, High Performance,” Microdesign Resources, Jun. 2000, Microprocessor Report, 4 pages.
Broadcom Corporation
Han Jessica
Merkel Lawrence J.
Meyertons Hood Kivlin Kowert & Goetzel P.C.
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