Static information storage and retrieval – Floating gate – Multiple values
Reexamination Certificate
1999-11-05
2001-08-21
Nelms, David (Department: 2818)
Static information storage and retrieval
Floating gate
Multiple values
C365S185210
Reexamination Certificate
active
06278633
ABSTRACT:
BACKGROUND
1. Field of the Invention
This invention relates to architectures and methods for writing a data set to and reading a data set from a non-volatile semiconductor memory such as a Flash memory.
2. Description of Related Art
Portable systems often use non-volatile semiconductor memory such as Flash memory for data storage. Such solid-state memories are compact, low cost, have low power requirements, and can retain data without any applied power. Some recent advances in non-volatile memory have been in multi-level non-volatile memories. Multi-level non-volatile memories store multiple digital bits of information or an analog level/value in each memory cell. Accordingly, multi-level non-volatile memories store more data per IC chip area and have lower cost per bit of data storage than do binary non-volatile memory. However, write and read operations for multi-level non-volatile memories are often slower than write and read operations in binary memories. Accordingly, the bandwidth or data rate for write and read operations in multi-level non-volatile memory may be insufficient for some applications.
One exemplary use of non-volatile memory is in a “digital” (or solid state) camera. A digital camera contains an imaging system that records or stores images as pixel data (i.e., an array of pixel values) in semiconductor memory. Each pixel value indicates a color of a small area (or pixel) in an image and can be stored in digital or analog form, depending on the type of semiconductor memory. When a picture is taken, the camera nearly instantaneously has a large quantity of pixel data to store. A record operation writes the pixel values to the memory array. Ideally, the bandwidth for writing to the memory is high enough to store an image as the pixel values are generated from or by the image sensor (CCD or CMOS) or at least before a user wants to take another picture. For recording of video images, the bandwidth for write operations of the memory must be sufficiently high to record one image after another at the frame rate of the video image. Downloading an image from the camera requires reading pixel values out of the memory a rate selected for data transfer.
Audio recording in a non-volatile memory stores a data series made of audio samples. Again, the bandwidth of the non-volatile memory must be high enough to store the audio samples at the sampling rate of the audio. Playing back the audio requires reading the samples at the sampling rate and converting the series of samples to a continuous audio signal. High quality audio recording generally requires a high sampling rate and memories with corresponding bandwidths. For CD quality audio recording and playback, the write and read bandwidths should match a sampling frequency of about 44 kHz.
U.S. Pat. No. 5,680,341, entitled “Pipelined Record and Playback for Analog Non-Volatile Memory”; U.S. Pat. No. 5,969,986, entitled “High-Bandwidth Read and Write Architecture for Non-Volatile Memories”; U.S. Pat. No. 6,134,145, entitled “High Data Rate Write Process for Non-volatile Flash Memories”; and U.S. Pat. 6,134,141, entitled “Dynamic Write Processes for High Bandwidth Multi-Bit-Per-Cell and Analog/Multi-Level Non-Volatile Memories”, which are hereby incorporated by reference in their entirety, describe use of pipelined memory accesses to achieved a high bandwidth data accesses in non-volatile memories.
A primary concern in multi-level non-volatile memory is the precision with which values are written and read. In particular, the precision with which write or read processes can set or determine a threshold voltage in a multi-bit-per-cell non-volatile memory cell determines the number of distinguishable values or states (e.g., the number of bits) that the non-volatile memory cell can store and retrieve. The write and read precision in an analog memory similarly determines the storage error and how accurately different analog levels can be reproduced. For optimal precision during a write and read operation, the voltage sources and operating conditions of the memory should be stable.
Writing of a threshold voltage generally achieves maximum precision by using the maximum available time for the write operation. One process for writing a multi-level (i.e., multi-bit or analog) value includes iterative program cycles and verify cycles. During each program cycle, the write process applies programming voltages to the source, drain, and control gate of a floating gate transistor in a selected memory cell. The programming voltages change the threshold voltage in the memory cell, for example, by channel hot electron injection. During each verify cycle, the write process determines whether the threshold voltage in the memory cell has reached a target threshold voltage corresponding to a multi-level value being written. This write process can distinguish two target threshold voltages (and corresponding multi-level values) if the difference in the target threshold voltages is greater than the threshold voltage change during a single program cycle. Accordingly, to maximize precision, the change in threshold voltage per program cycle should be minimized. Short program cycles and a low gate voltage, selected for example according to the target threshold voltage, can decrease change in threshold voltage per program cycle. However, the number of program and verify cycles and the total write time increase as the threshold voltage change per program cycle decreases. The available write time or the required write bandwidth thus limits the number of program cycles and the minimum threshold voltage change per program cycle.
Ideally, the change per program cycle is such that the maximum number of program and verify cycles required during a write takes all of (but not more than) the available times for a write operation. This is difficult to achieve because memory cells may vary from one array to the next and from one chip to the next. Accordingly, memory cells do not respond in the same fashion to program cycles. Further, a memory cell's response to a program cycle changes over the life of the memory cell because of charge-trapping around a floating gate in the memory cell. Accordingly, designers of multi-level non-volatile memories have chosen write voltages and program cycles that satisfy expected conditions during the life of a non-volatile memory. However, the chosen write voltages and program cycles often fail to provide optimum precision in the available write time.
Makers of non-volatile memory are now striving to achieve maximum write and read precision in the short times available in high bandwidth multi-level non-volatile memories.
SUMMARY
In accordance with an aspect of the invention, a multi-level non-volatile memory includes one or more arrays of memory cells with each array including one or more dummy cells. Measurements of write operations to the dummy cells indicate the reaction that the memory cells have to the programming voltages. After, writing to one or more dummy cells, the parameters such as the programming voltages or the duration of program cycles are adjusted to optimize the precision of a write operation in the available write time.
In accordance with another aspect of the invention, a multi-level non-volatile memory includes multiple arrays of memory cells and pipelined memory accesses to achieve a high bandwidth I/O processes for data streams. A shared charge pump or other shared voltage source provides uniformity for a write or read voltage used when accessing memory cells in the arrays. To improve stability of record and playback operations, each array includes at least one dummy memory cell, and pipelined access of storage cells begins by accessing the dummy cells. Writing or reading of actual data does not begin until reaching a steady state where the shared charge pump or voltage supply is driving a constant number of pipelined operations in various stages. Similarly, when ending a record or playback operation, the memory continues accessing (writing or reading) dummy information so that accesses of actual data fini
So Hock C.
Wong Sau C.
Millers David T.
Multi Level Memory Technology
Nelms David
Tran M.
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