High bandwidth datapath load and test of multi-level memory...

Details High bandwidth datapath load and test of multi-level memory... High bandwidth datapath load and test of multi-level memory...

2006-07-11

2006-07-11

Elms, Richard (Department: 2824)

Static information storage and retrieval

Floating gate

Multiple values

C365S201000, C365S185330, C365S189070, C365S185220

Reexamination Certificate

active

07075822

ABSTRACT:
An apparatus and technique for testing of multi-level cells (MLC) in a memory storage device using a high bandwidth data path architecture. The technique includes hardware for obtaining a first data and a second data from a multilevel cell memory. The first data is different from the second data. The first data and second data are compared and, based at least in part on this comparison, the multilevel cell memory is programmed. Programming the multilevel cell memory includes accessing memory cells in the multilevel cell memory and determining the number of bits per memory cell of the first data that need programming.

REFERENCES:
patent: 5768287 (1998-06-01), Norman et al.
patent: 5907700 (1999-05-01), Talreja et al.
patent: 5944837 (1999-08-01), Talreja et al.
patent: 6493270 (2002-12-01), Chevallier
patent: 6836431 (2004-12-01), Chang
patent: 2001/0040826 (2001-11-01), Lakhani

Affiliated with

Also associated with

Rating

High bandwidth datapath load and test of multi-level memory... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with High bandwidth datapath load and test of multi-level memory..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and High bandwidth datapath load and test of multi-level memory... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3554143