Active solid-state devices (e.g. – transistors – solid-state diode – Integrated circuit structure with electrically isolated... – Including dielectric isolation means
Reexamination Certificate
1998-01-14
2001-10-30
Lee, Eddie (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Integrated circuit structure with electrically isolated...
Including dielectric isolation means
C257S501000, C257S506000
Reexamination Certificate
active
06310385
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to junction isolation of high voltage power integrated circuits and, more specifically, relates to improving heat dissipation in high voltage power integrated circuits by using a high (wide) band-gap material as an insulating layer.
Currently, most high voltage integrated circuits are designed and manufactured using junction isolation. Some of the problems that are associated with junction isolation include: (i) difficulty in integrating lateral bipolar devices without parasitic current flow in the substrate material; (ii) likelihood of “latch-up” in CMOS circuits when high dv/dt conditions are present, such as during high voltage switching; and (iii) relatively high leakage current flow in the junction materials at high ambient temperatures.
Dielectric isolation mitigates the above problems. However, the dielectric isolation introduces other problems, such as difficulty in providing heat dissipation through the dielectric isolation material as well as wafer-warpage due to the thick oxides needed to vertically support high-voltage.
Accordingly, a need exists in the electronic semiconductor device art for a structure which provides dielectric isolation that mitigates the problems encountered using junction isolation, which provides adequate heat dissipation of the semiconductor devices irrespective of the dielectric isolation material used and which is not susceptible to wafer-warpage.
SUMMARY OF THE INVENTION
The present invention overcomes the problems associated with the prior art by providing an integrated circuit in which a relatively low band gap material is used as a semiconductor device layer and in which a semi-insulating, underlying high (wide) band gap material is used as a thermally conducting, electrically insulating layer.
The insulating material, which, for example, may be silicon carbide, gallium nitride, semi-insulating polysilicon, amorphous silicon, beryllium oxide or aluminum oxide, is a material of high thermal conductivity to avoid the problem of heat dissipation while attaining the advantages of dielectric isolation.
The heterojunction between the high band gap material and the low band gap semiconductor provides a barrier to current flow whose height depends on the band-gap difference, the electron-affinity difference and the doping type of the two materials and which provides isolation between the respective devices on an integrated circuit.
In a preferred embodiment, the integrated circuit includes one or more semiconductor wells which are each surrounded on their sides by an insulator material such as silicon dioxide. The insulator material effectively insulates the adjacent semiconductor wells from each other.
The bottoms of the semiconductor wells are disposed atop a high band-gap material which provides high thermal conductivity that allows heat to dissipate. Electrical isolation is provided by the heterojunction between the high band-gap and low band-gap semiconductor materials.
A semiconductor substrate may be provided to support the high band-gap material. Also, a layer of insulation material may be provided between the high band-gap material and the semiconductor substrate. Polycrystalline silicon or a low carrier lifetime semiconductor material may be used instead of the high band-gap material. Also, vertical power devices may be integrated with lateral high voltage power devices, CMOS devices and other analog circuit elements in the integrated circuit of the present invention.
Other features and advantages of the present invention will become apparent from the following description of the invention which refers to the accompanying drawings.
REFERENCES:
patent: 3290753 (1966-12-01), Chang
patent: 3838441 (1974-09-01), Bean et al.
patent: 4238762 (1980-12-01), McWilliams et al.
patent: 4242697 (1980-12-01), Berthold et al.
patent: 4310965 (1982-01-01), Horiuchi et al.
patent: 4755859 (1988-07-01), Suda et al.
patent: 4918498 (1990-04-01), Plus et al.
patent: 4920396 (1990-04-01), Shinohara et al.
patent: 4984052 (1991-01-01), Koshino et al.
patent: 5155571 (1992-10-01), Wang et al.
patent: 5241211 (1993-08-01), Tashiro
patent: 5336904 (1994-08-01), Kusunoki
patent: 5362667 (1994-11-01), Linn et al.
patent: 5378923 (1995-01-01), Mitsui et al.
patent: 5385855 (1995-01-01), Brown et al.
patent: 5396085 (1995-03-01), Baliga
patent: 5406096 (1995-04-01), Malhi
patent: 5408106 (1995-04-01), Seabaugh
patent: 5461253 (1995-10-01), Tsuruta et al.
patent: 5471083 (1995-11-01), Ikeda et al.
patent: 5561303 (1996-10-01), Schrantz et al.
patent: 5714775 (1998-02-01), Inoue et al.
patent: 5723896 (1998-03-01), Yee et al.
patent: 5726478 (1998-03-01), Gantioler et al.
patent: 5737671 (1998-04-01), Watanabe
patent: 5757081 (1998-05-01), Chang et al.
patent: 5767562 (1998-06-01), Yamashita
patent: 5847419 (1998-12-01), Imai et al.
Wolf, Semiconductors, p. 33, 1971.
Baumeister Bradley William
International Rectifier Corp.
Lee Eddie
Ostrolenk Faber Gerb & Soffen, LLP
LandOfFree
High band gap layer to isolate wells in high voltage power... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with High band gap layer to isolate wells in high voltage power..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and High band gap layer to isolate wells in high voltage power... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2605770