Boots – shoes – and leggings
Patent
1989-08-21
1991-05-28
Harkcom, Gary V.
Boots, shoes, and leggings
364243, 3642434, 36424341, G06F 930
Patent
active
050199714
ABSTRACT:
A high availability set associative cache memory for use as a buffer between a main memory and a central processing unit includes multiple sets of cache cells contained in two or more cache memory elements. Each of the cache cells includes a data field, a tag field and a status field. The status field includes a force bit which indicates a defective cache cell when it is set. Output from a cache cell is suppressed when its force bit is set. The defective cache cell is effectively mapped out so that data is not stored in it. As long as one cell in a set remains operational, the system can continue operation. The status field also includes an update bit which indicates the update status of the respective cache cell. Replacement selection logic examines the bit pattern in all the cache cells in a set and selects a cache cell to be replaced using a first-in first-out algorithm. The state of the update bit is changed each time the data in the respective cache cell is replaced unless the cache cell was modified on a previous store cycle.
REFERENCES:
patent: 4095283 (1978-06-01), Campbell et al.
Motorola MC68020 32-Bit Microprocessor User's Manual, 1985, pp. 7-1 thru 7-4.
Patent Abstracts of Japan, vol. 10, No. 86, JP-A-60221855, Hitachi Seisakusho K.K., 11-6-1985.
IBM Technical Disclosure Bulletin, vol. 25, No. 12, May 1983, pp. 6503-6509, D. E. Doyle: "Redundant LRU Encoding for Cache Directories".
Lefsky Brian
Natusch Mary E.
Harkcom Gary V.
Jaffe Michael A.
Prime Computer Inc.
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