High aspect ratio low resistivity lines/vias with a tungsten-ger

Details High aspect ratio low resistivity lines/vias with a tungsten-ger High aspect ratio low resistivity lines/vias with a tungsten-ger

1996-10-28

1998-03-24

Kunemund, Robert

Semiconductor device manufacturing: process

Chemical etching

Altering etchability of substrate region by compositional or...

438693, 438697, 438752, 438754, H01L 21302

Patent

active

057312451

ABSTRACT:
A structure and method for fabricating circuits which use field effect transistors (FETs), bipolar transistors, or BiCMOS (combined Bipolar/Complementary Metal Oxide Silicon structures), uses low temperature germanium gas flow to affect metals and alloys deposited in high aspect ratio structures including lines and vias. By using a germanium gas flow, germanium (Ge) will be introduced in a surface reaction which prevents voids and side seams and which also provides a passivating layer of CuGe. If a hard cap is needed for surface passivation or a wear-resistance application, the GeH.sub.4 gas followed by WF.sub.6 can be used to produce an in-situ hard cap and polish stop of W.sub.x Ge.sub.y, a tungsten-germanium alloy. Further, high aspect ratio vias/lines (aspect ratio of 3 or more) can be filled by utilizing low pressures and high temperatures (i.e., below 450.degree. C.) without degrading the underlying metals.

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