High aspect ratio fill method and resulting structure

Details High aspect ratio fill method and resulting structure High aspect ratio fill method and resulting structure

2003-03-03

2004-06-29

Potter, Roy (Department: 2822)

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Of specified configuration

C257S763000, C257S766000

Reexamination Certificate

active

06756682

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates generally to semiconductor devices, and more specifically to processes for deposition and filling of contact areas in semiconductors. In particular, this invention relates to processes used to fill via contact regions.
BACKGROUND
With reduction in the size and dimensions of transistor features, more components are placed on each chip, which increases the complexity of the fabrication process as well as contact densities and aspect ratios.
The ever increasing circuit density has also resulted in increasing aspect ratios for various structures formed during the manufacture of integrated circuits. Particularly for such structures as contacts and vias, higher aspect ratios have had a negative effect on fabrication yields. Aspect ratio is defined herein as the height/width ratio of a feature.
Adequate filling of high aspect ratio contacts and vias using previous employed methods has been somewhat difficult to achieve. Previous attempts at filling contacts, in particular contacts with high aspect ratios, often produce contacts with void spaces, also termed keyholes. These keyholes are problematic in that they are known to affect the conductivity of the contact and may also deform fabricated structures.
Previous techniques have attempted to address the problems associated with keyhole formation, for example the use of chemical vapor deposition of metals (CVD), and laser reflow and aluminum reflow methods. These techniques, however, do not entirely solve the problems associated with keyhole formation. In particular, as the aspect ratio increases, metal deposited at colder temperatures fails to produce good step coverage due to “necking” (or “cusping”) at the top corners of contacts. The use of flared or tiered corners for the vias has also been utilized, however, altering the geometry of via corners often results in the loss of semiconductor area. Use of a partially ionized beam (PIB) to deposit a metal layer is often not practical due to low deposition rates which reduces throughput and increases the risk of gaseous inclusion into the metal layer. In multi-step metallization processes, keyholes often form if insufficient metal is deposited. Keyhole formation is also problematic using directed vapor deposition (DVD) for several reasons, including negative effects on the conductivity of the channel and deformation of metals in the transistor components of the semiconductor.
For example, known methods for creating contacts in high aspect ratio vias have often involved filling the holes with deposited metal layers such as a sequentially layered stack of titanium (Ti), titanium nitride (TiN) and tungsten (W), i.e. a W/TiN/Ti stack. However, filling of high aspect ratio via holes with common stack of W/TiN/Ti produces keyholes. Electroless processes for filling of a high aspect ratio contact utilizing nickel (Ni) or cobalt (Co) have also been found to produce undesirable keyhole formation.
Consequently, a need exists for a practical and efficient method for filling high aspect ratio contacts. In particular, a need exists for a low cost and efficient process that may be used to fill high aspect contacts in a void-free manner.
SUMMARY OF THE INVENTION
The present invention provides a method for producing contacts in high aspect ratio vias or holes which have fewer or no voids using a bottom-up electroless plating technique. The method comprises forming an insulating layer over a semiconductor substrate; forming an opening in the insulating layer to an area containing silicon; depositing a conductive material within the opening; forming a silicide layer at the interface of the conductive material and the area containing silicon; removing the conductive material from the opening while leaving the silicide layer; and forming a conductor within the opening by electroless plating over the silicide layer.
In another aspect, the invention is directed to a semiconductor structure comprising a semiconductor substrate having an insulating layer over said semiconductor substrate; an opening in said insulating layer to an area containing silicon; a silicide layer formed at the interface of said opening and said area containing silicon; and an electrolessly plated conductor formed over said silicide layer within said opening.


REFERENCES:
patent: 4692349 (1987-09-01), Georgiou et al.
patent: 5169680 (1992-12-01), Ting et al.
patent: 5308796 (1994-05-01), Feldman et al.
patent: 5888903 (1999-03-01), O'Brien
patent: 5913147 (1999-06-01), Dubin et al.
patent: 5969422 (1999-10-01), Ting et al.
patent: 5985103 (1999-11-01), Givens et al.
patent: 6180469 (2001-01-01), Pramanick et al.
patent: 6297156 (2001-10-01), Farrar et al.
patent: 6326303 (2001-12-01), Robinson et al.
patent: 6331482 (2001-12-01), Honeycutt et al.
patent: 6359328 (2002-03-01), Dubin
patent: 2002/0127790 (2002-09-01), Hongo et al.
patent: 2-50432 (1990-02-01), None

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