High accuracy MOS comparator

Electrical transmission or interconnection systems – Personnel safety or limit control features – Interlock

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307279, 307DIG1, 307DIG3, 328165, 330 35, H03K 520, H03K 3353, H03F 316, H04B 1500

Patent

active

040285588

ABSTRACT:
The voltages to be compared are applied to a passive MOS capacitor differencing circuit for producing a voltage difference signal, which then is amplified by a high-gain non-precision FET amplifier, the output of which is passed through a low output impedance FET buffer amplifier to a FET latching circuit. Capacitive coupling is used for enabling the amplifiers to be independently biased and to eliminate D.C. offsets. The operating cycle of the comparator has two periods. During an initial set-up or preconditioning period the amplifiers are self-biased by appropriate switching actions which cause each of the amplifiers to be set at a desired operating point that is maintained when its respective bias switching connection subsequently is opened. The bias switch openings in the respective amplifier and latching stages are timed to occur in a chosen sequence which causes the switching transients to be absorbed. At the end of the preconditioning period, the comparator is set up for operation in the comparison period during which the input signals are compared.

REFERENCES:
patent: 3191124 (1965-06-01), Brown
patent: 3588537 (1971-06-01), Brink
patent: 3676702 (1972-07-01), McGrogan, Jr.
patent: 3976952 (1976-08-01), Shaver
patent: 3983413 (1976-09-01), Gunsagar et al.
patent: 3993917 (1976-11-01), Kalter

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