High accuracy, high speed, low power analog-to-digital...

Details High accuracy, high speed, low power analog-to-digital... High accuracy, high speed, low power analog-to-digital...

1999-02-03

2001-01-23

Williams, Howard L. (Department: 2819)

Coded data generation or conversion

Analog to or from digital conversion

Analog to digital conversion

C341S155000

Reexamination Certificate

active

06177901

ABSTRACT:

BACKGROUND OF THE INVENTION
This invention relates to a method and apparatus for analog-to-digital conversion. More particularly, the invention relates to a high accuracy, high speed, low power analog-to-digital conversion method and circuit.
The importance of high accuracy and speed, as well as low power consumption in an analog-to-digital converter (“ADC”) is well known. This need is especially great in CMOS circuitry, where it is desirable to integrate ADC circuits with digital circuits on the same substrate. While some efforts have been made to integrate ADC circuits with digital circuits on the same CMOS substrate, the technology thus far has had serious drawbacks. Flash ADCs, discussed below, have been used to achieve high speed digital-to-analog conversion on a CMOS digital substrate, but suffer from mismatch errors, among other things. Pipeline ADC's, wherein high speed is achieved by using multiple segmented stages require linear capacitors that are difficult and expensive to realize.
There are several basic approaches to analog-to-digital conversion, and many variations thereof. One approach, known as charge integration conversion, works by sampling the analog signal, charging a capacitor with the sample, then discharging the capacitor at a known rate while counting the time it takes to discharge. The time is proportional to the sampled voltage. This approach is disclosed in LeChevalier U.S. Pat. No. 4,998,109 (“LeChevalier”) and Kogan U.S. Pat. No. 5,298,902. A more sophisticated variation of this approach, known as dual-slope conversion, charges a capacitor for a known, controlled period of time before discharging the capacitor at a constant rate. Examples of this approach are disclosed in Hopkins U.S. Pat. No. 5,614,902; Liao U.S. Pat. No. 5,592,168; and George et al. U.S. Pat. No. Re. 34,428. While these methods can be very accurate, they are also relatively slow because the average time required is proportional to the number of levels the converter must resolve.
Another approach, similar to the charge integration approach, works by comparing a sample of the input signal to a reference signal whose amplitude varies with time in a known way, typically a ramp with a constant slope, and counting the time until the level of the reference signal is substantially equal to the level of the sample. That time is proportional to the level of the sample. Examples of this approach are disclosed in Cuthbert et al. U.S. Pat. No. 3,737,897 and Mallinson et al. U.S. Pat. No. 5,321,404. Like the charge integration approach, this “slope comparison” approach can produce very accurate results but is relatively slow. In addition, this approach has the drawback that it is susceptible to drift with temperature variations which change the manner in which the reference signal varies with time, such as by changing the slope of a ramp reference.
High speed analog-to-digital conversion can generally be achieved by an approach known as flash conversion. In this approach a plurality of comparators simultaneously compare the analog signal to each of the voltage levels to be resolved. This approach is described in LeChevalier. Some drawbacks of flash conversion are that it requires a large number of comparators which are expensive and increasingly impractical with increasing resolution, and that one analog signal drives many comparators, so expensive buffering is required to provide the necessary power.
A compromise on speed can be achieved using a successive approximation approach. In this approach, the analog signal is sampled and the sample is compared sequentially to successively closer values using a single comparator. An example of successive approximation is disclosed in Van Auken et al. U.S. Pat. No. 5,638,072. Successive approximation requires less circuitry and is faster than charge integration for the same resolution, but is much slower than flash conversion.
It would be desirable to employ an analog-to-digital conversion approach that achieves accuracy comparable to charge integration, without the drift problem of slope comparison, and achieves speed comparable to flash conversion.
In addition, all of the known approaches to digital-to-analog conversion employ comparators, which have inherent offset that introduces error. It would be desirable to substantially eliminate that error with minimal additional circuitry, particularly for integration with CMOS digital technology.
Accordingly, there is a need for a high accuracy, high speed, low power analog-to-digital conversion method and circuit.
SUMMARY OF THE INVENTION
The present invention solves the aforementioned problems and meets the aforementioned needs by (1) providing for simultaneous comparisons of a plurality of signal samples with a time varying scan signal, (2) sampling and converting references voltages as well as signal samples, (3) splitting the conversions into coarse and fine parts, and (4) canceling out any offset induced error. The input signal samples may be sampled from one analog input signal, or from multiple analog input signals.
Basically, a sample of an input signal which it is desired to convert to digital form has a value A
input
. The scan signal ranges over all the anticipated values of A
input
. The time, T
scan
, when A
scan
reaches A
input
is determined. Preferably, such scan times are determined for a plurality of samples A
input
(k) of the input signal.
Further, at least two reference voltages V
ref1
and V
ref2
are compared against the scan signal, and the times t
ref1
and t
ref2
where A
scan
reaches of V
ref1
and V
ref2
are determined, and coordinates (V
ref1
, t
ref1
) and (V
ref2
, t
ref2
) are obtained. A sufficient number of coordinates are obtained to fully characterize the scan signal. For example, where the scan signal is linear, two coordinates fully characterize the scan signal.
In another aspect of the invention, a “two-step” conversion is provided. In a first stage or step of the conversion, a coarse determination of A
input
, A
coarse
, is obtained in like manner to that described above, wherein a first set of coordinates sufficient to define the scan signal are selected that approximately bound the full, anticipated input signal range. The coarse determination finds the most significant bits of A
input
.
In a second stage or step of the analog-to-digital conversion, a fine determination of A
input
,A
fine
, is obtained in like manner to that described above; however, a second set of reference values are selected with knowledge of A
coarse
so that a significantly smaller range may be employed for the scan signal than the entire anticipated signal range.
The two-step method may be performed by a single stage operating in series, or by a plurality of stages forming a pipeline.
In a further aspect of the invention, comparator offset is substantially eliminated by converting the sample twice in consecutive steps. In a first conversion, the input and scan signals are provided to respective inputs that are inverting and non-inverting. In a second conversion, the inputs to the comparator are reversed and output negated. The results of both comparisons are averaged to cancel out comparator input offset.
Accordingly, it is a principal object of the present invention to provide a novel analog-to-digital conversion method and circuit.
It is another object of the present invention to provide such an analog-to-digital conversion method and circuit that provides for higher accuracy, higher speed and more efficient power consumption.
It is still another object of the invention to provide an accurate, high speed analog-to-digital converter circuit that can be integrated into low power CMOS digital circuit substance.
The foregoing and other objects, features and advantages of the invention will be more readily understood upon consideration of the following detailed description of the invention, taken in conjunction with the following drawings.


REFERENCES:
patent: Re. 34428 (1993-11-01), George et al.
patent: 3609756 (1971-09-01), Murrell et al.
patent: 3737897 (1973-06-01), Cuthbert et a

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