High accuracy comparator

Details High accuracy comparator High accuracy comparator

1999-11-08

2001-09-11

Williams, Howard L. (Department: 2819)

Coded data generation or conversion

Analog to or from digital conversion

Analog to digital conversion

C327S052000

Reexamination Certificate

active

06288666

ABSTRACT:

FIELD OF THE INVENTION
This invention is generally related to analog electronics and more particulary to comparators manufactured by a metal oxide semiconductor (MOS) process.
BACKGROUND
The comparator is an essential component of almost every mixed analog-digital circuit application. The ideal comparator should be small, fast, accurate, consume low power, and operate over a wide range of input signal level. A relatively small, fast, low power comparator that can be built using a MOS process is described in U.S. Pat. No. 5,274,275 issued to Colles (“Colles”). The Colles comparator features a single differential input stage with a dual purpose load. The load is under the control of an external signal. It allows the differential input stage to initially preamplify the input signals at the output of the input stage, and then operates as a regenerative latch to drive the output at a higher gain. The initial preamplify phase provides high accuracy by distinguishing between input signals that are relatively close in value, while the regenerative/latch phase completes the comparison at a greater speed.
One of the limitations of the Colles comparator is its relatively low accuracy, despite the use of the preamplify phase, due to offsets caused by device mismatching in the manufactured version of the circuit. In conventional comparators, various offset cancellation techniques are typically used to compensate for such offsets, and thereby enable the comparator to resolve a difference in the input signals which is smaller than the offset, thus yielding a “higher resolution” or more accurate comparison. Two of the most common approaches to offset cancellation are input offset storage and output offset storage. See Design
Techniques for High-Speed. High Resolution Comparators
, Razavi and Wooley, IEEE Journal of Solid-State Circuits, Vol. 27, No. 12, December 1992 (“Razavi”);
Integrated Analog-to-Digital and Digital-to-Analog Converters
, Rudy van de Plassche, Kluwer Academic Publishers, pp. 126-128 (“Plassche”). In both of these techniques, an offset voltage is sensed, stored, and then subtracted from the input to achieve cancellation.
Razavi discloses multi-stage comparators in which the output of a preamplifier stage is connected to an input of a latch, so that the comparator output is the latch output. Razavi, FIG.
1
(
a
). The offset, which is a combination of the input offset of the preamplifier and the latch offset, is first stored on a pair of capacitors that are coupled to the inputs of the preamplifier at one end and to common ground at another, by closing a unity-gain loop around the preamplifier. The cancellation of offset is then performed by opening switches that connect one end of the capacitors to ground, and then applying the input signals to the capacitors. The offset previously stored in the capacitors is thus subtracted from the respective input signals, thus canceling the offset.
In Razavi, the input offset storage techniques are applied to multi-stage comparators as compared to the single stage, Colles comparator, the difference being that in Razavi the output of the comparator following the latch stage is not the same as the output of the preamplifier. Moreover, the offset cancellation techniques in Razavi may tend to inject excessive switch noise and ground noise into the storage capacitors via switches that connect one end of the capacitors to ground. This noise prevents the accurate capture of the true offset voltages.
SUMMARY
An embodiment of the invention is directed to a comparator which includes a differential amplifier having first and second inputs and first and second outputs. A first switch is to couple the first input to the first output. A second switch is to couple the second input to the second output. A first storage device is coupled to the first input at one end and is to receive a first input signal at another end. A second storage device is coupled to the second input at one end and is to receive at another end the first input signal during a first time interval. Thereafter, a second input signal to be compared with the first input signal is applied to the second storage device.


REFERENCES:
patent: 4408133 (1983-10-01), Cooperman et al.
patent: 5032744 (1991-07-01), Wai Yeung Liu
patent: 5274275 (1993-12-01), Colles
patent: 5563533 (1996-10-01), Cave et al.
patent: 5912567 (1999-06-01), Drost et al.
patent: 5955899 (1999-09-01), Afghahi
patent: 6008673 (1999-12-01), Glass et al.
Behzad Razavi & Bruce A. Wooley, “Design Techniques for High-Speed, High-Resolution Comparators”; IEE Journal of Solid State Circuits, vol. 27, No. 12.
Rudy van de Plassche, “Integrated Analog-To-Digital and Digital-To-Analog Converters”, Kluwer Academic Publishers, pp. 126-129.

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