Hierarchy structured memory system contained in a multiprocessor

Details Hierarchy structured memory system contained in a multiprocessor Hierarchy structured memory system contained in a multiprocessor

1990-05-30

1993-05-25

Richardson, Robert L.

395425, 395400, G06F 1326

Patent

active

052147754

ABSTRACT:
A multiprocessor having a plurality of processor elements connected in a cascaded manner. A memory is shared between each processor element and a processor adjacent in an upper or lower rank to the processor. In the lower processor element, there are disposed an arbiter for arbitrating a memory access with its upper processor element and a bus selector for switching a bus with the arbiter. The processor elements are connected in a multistage tree structure by a bus connection only. From the upper processor element, therefore, there can be accessed the shared memory in the lower processor element only through an external bus. The whole system is not limited by the address space of each processor and the bus, even if the address space is finite, so that the real memory capacity can be limitlessly expanded in a manner to correspond to the internal memory of each processor element.

REFERENCES:
patent: 4550368 (1985-10-01), Bechtolsheim
patent: 4827406 (1989-05-01), Bischoff et al.

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