Hierarchical word line structure

Details Hierarchical word line structure Hierarchical word line structure

1998-02-17

1999-08-24

Nelms, David

Static information storage and retrieval

Addressing

Particular decoder or driver circuit

36518523, G11C 800

Patent

active

059432896

ABSTRACT:
A hierarchical word line structure for a semiconductor memory is provided that substantially eliminates coupling noise between neighboring wiring lines by driving neighboring sub-word lines by different main word lines. The hierarchical word line structure further reduces a layout size. The hierarchical word line structure uses one less transistor than a related art sub-word line driver. The word line includes a plurality of word line rows that each include a plurality of sub-word line drivers. The sub-word line drivers receive sub-word line driver enable signals among which only one signal becomes high level at a time. Each of the word line rows correspond to a main word line and a subset of the plurality of sub-word line drivers that drive neighboring sub-word lines are coupled to different respective main word lines.

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T. Sugibaysahi, et al., "A 30ns 256Mb DRAM with Multi-Divided Array Structure", IEEE International Solid-State Circuits Conference, Non-Volatile, Dynamic, an Experimental Memories/Papers, pp. 50-51 and 262, 1993.

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