Data processing: structural design – modeling – simulation – and em – Simulating electronic device or electrical system
Reexamination Certificate
2005-08-12
2010-02-02
Rodriguez, Paul L (Department: 2123)
Data processing: structural design, modeling, simulation, and em
Simulating electronic device or electrical system
C706S921000, C716S030000
Reexamination Certificate
active
07657416
ABSTRACT:
A method of system design, and more particularly a method of designing systems that achieve a set of performance goals using a hierarchically partitioned system representation wherein performance simulations are performed at multiple levels within the hierarchy and are combined to simulate a system level result in order to reduce the aggregate time required for performance simulation.
REFERENCES:
patent: 5553002 (1996-09-01), Dangelo et al.
patent: 6442743 (2002-08-01), Sarrafzadeh et al.
patent: 6687887 (2004-02-01), Teig et al.
patent: 6694501 (2004-02-01), Chang et al.
patent: 6957400 (2005-10-01), Liu et al.
patent: 7370295 (2008-05-01), Chesal et al.
patent: 7437343 (2008-10-01), Josephson et al.
patent: 2004/0111679 (2004-06-01), Subasic et al.
patent: 2004/0153294 (2004-08-01), McConaghy
patent: 2004/0243962 (2004-12-01), Subasic et al.
patent: 2005/0200623 (2005-09-01), Smith et al.
patent: 2005/0257178 (2005-11-01), Daems et al.
patent: 2006/0015829 (2006-01-01), De Smedt et al.
Nagasamy et al, “Specification, Planning and Synthesis in a VHDL Design Environment”, IEEE Design and Test of Computers, vol. 9, Issue 2, pp. 58-68, Jun. 1992.
Alliot et al, “Architecture Exploration of a Large Scale System”, Proceedings of the 5th IEEE International Workshop on Rapid System Prototyping, 2004.
Sobiezczanski-Sobieski et al, “Multidisciplinary Aerospace Design Optimization: Survey of Recent Developments”, Structural and Multidisciplinary Optimization, vol. 14, No. 1, Aug. 1997.
Eeckhout et al, “Workload Design: Selecting Representative Program Input-Pairs”, Proceedings of the 2002 International Conference on Parallel Architectures and Compilation Techniques (PACT '02), 2002.
Chien et al, “Designer Driven Topology Optimization for Pipelined Analog to Digital Converters”, Proceedings of the Design, Automation and Test in Europe Conference and Exhibition, Mar. 7-11, 2005.
Zhang et al, “Automatic Synthesis of a 2.1 GHz SiGe Low Noise Amplifier”, IEEE Radio Frequency Integrated Circuits Symposium, Jun. 2-4, 2002.
De Smedt et al, “WATSON: Design Space Boundary Exploration and Model Generation for Analog and RF IC Design”, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 22, No. 2, Feb. 2003.
McFarland, “Using Bottom-UP Design Techniques in the Synthesis of Digital Hardware from Abstract Behavioral Descriptions”, 23rd Design Automation Conference, Papers on Twenty-five years of Electronic Design Automation, pp. 602-608, 1988.
Rao et al, “Hierarchical Design Space Exploration for a Class of Digital Systems”, IEEE Transactions on Very Large Scale Integrated (VLSI) Systems, vol. 1, No. 3, Sep. 1993.
Andersen, E. et al., “A direct search algorithm for optimization with noisy function evaluations”, Siam J. Optim., vol. 11, No. 3, Feb. 2001, p. 837-857.
Fonseca, C., et al., “Multiobjective optimization and multiple constraint handling with evolutionary algorithms”, IEEE Transactions on Systems, vol. 28, No. 1, (1998), p. 38-47.
Kolda, T. et al., “Optimization by direct search: new perspectives on some classical and modern methods”, SIAM Review, vol. 45, No. 3, (2003) p. 385-482.
Miranda, V et al., “EPSO—evolutionary particle swarm optimization, a new algorithm with applications in power systems”, IEEE (2002), p. 745-750.
Smith, L., “A tutorial on principal components analysis”, http://www.cs.otago.ac.nz/cosc453/student—tutorials, Feb. 26, 2002, p. 1-26.
Zitzler, E., “Multiobjective evolutionary algorithms: a comparative case study and the strength pareto approach”, IEEE Trans. on Evo. Compu, vol. 3, No. 4, (1999), p. 257-271.
Dengi Enis Aykut
Subasic Pero
Cadence Design Systems, Inc
Chan Thomas
Jacob Mary C
Rodriguez Paul L
Wheelock Chan LLP
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