Static information storage and retrieval – Addressing – Plural blocks or banks
Reexamination Certificate
2000-10-12
2001-09-18
Mai, Son (Department: 2818)
Static information storage and retrieval
Addressing
Plural blocks or banks
C365S063000, C365S205000, C365S208000
Reexamination Certificate
active
06292427
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Technical Field of the Invention
The present invention relates generally to semiconductor memories, and more particularly, to compilers for high-speed and high-density semiconductor memories having hierarchical sense amplifier (sense amp) and write driver circuitry.
2. Description of Related Art
Silicon manufacturing advances today allow true single-chip systems to be fabricated on a single die (i.e., System-On-Chip or SOC integration). However, there exists a “design gap” between today's electronic design automation (EDA) tools and the advances in silicon processes which recognizes that the available silicon real-estate has grown much faster than has designers' productivity, leading to underutilized silicon. Unfortunately, the trends are not encouraging: the “deep submicron” problems of non-convergent timing, complicated timing and extraction requirements, and other complex electrical effects are making silicon implementation harder. This is especially acute when one considers that analog blocks, non-volatile memory, random access memories (RAMs), and other “non-logic” cells are being required. The gap in available silicon capacity versus design productivity means that without some fundamental change in methodology, it will take hundreds of staff years to develop leading-edge integrated circuits (ICs).
Design re-use has emerged as the key methodology solution for successfully addressing this time-to-market problem in semiconductor IC design. In this paradigm, instead of re-designing every part of every IC chip, engineers can re-use existing designs as much as possible and thus minimize the amount of new circuitry that must be created from scratch. It is commonly accepted in the semiconductor industry that one of the most prevalent and promising methods of design re-use is through what are known as Intellectual Property (“IP”) components—preimplemented, re-usable modules of circuitry that can be quickly inserted and verified to create a single-chip system. Such re-usable IP components are typically provided as megacells, cores, macros, embedded memories through generators or memory compilers, et cetera.
It is well known that memory is a key technology driver for SOC design. It is also well known that the existing memory compilers are adequate for designing low density memory arrays e.g., up to 4 Mbit memories. However, as arrays get larger for higher density by increasing in the X-direction (by adding additional columns or bitlines), Y-direction (by adding additional rows or wordlines), or both, parameters such as RC time delay, etc., which have a deleterious effect on the performance of a memory circuit, become significant in both directions of an array. Accordingly, it is common practice in the memory design art to segment the array in the Y-direction in order to provide additional sense amplifiers (SA) and associated write driver (WD) circuitry (referred to as primary SA/WD circuitry) at predetermined locations across the memory array. That is, for every predetermined number of wordlines, a horizontal band or strip of sense amplifier/write driver circuitry is provided in the Y-direction of the array. Consequently, the RC delay effects in the Y-direction are mitigated because the total length of bitline per primary sense amplifier (i.e., “bitline segment”) is considerably reduced. This practice of segmenting the array vertically is sometimes referred to as “banking.”
It is also known in the art to segment the wordlines in order to reduce the RC delay effects along the X-direction of the array. Typically, a local wordline decoder is provided at specific locations in the memory array along the X-direction which receives main wordline signals from a main row decoder. The main wordline signals are then decoded by the local wordline decoder in order to select a particular local row or wordline (or, sub-word line). This scheme is known in the industry as the “divided wordline” or DWL architecture.
Although advances such as those described above attempt to address the RC delay effects in large memory arrays, several deficiencies and shortcomings continue to exist. For example, where the sizes of the devices comprising the primary SA/WD circuitry are required to be absolute minimum, which is ideal for both highest density and highest speed memory, the number of cells per bitline segment that the sense amp circuitry can effectively drive needs to be significantly reduced (e.g., 32 cells per segment) without incurring a severe area penalty (which results from the larger size devices required to drive). That is because, as the device sizes get larger, parasitic diode capacitance effects become significant and negatively impact the performance. In other words, there exists a sense amp size versus speed versus parasitic diode effect trade-off in larger arrays which cannot be adequately addressed by the existing SA/WD architectures. Further, merely increasing the number of primary SA/WD bands having minimum geometry devices does not effectively solve the problem. For a high speed 16 Mbit compiler (with 4 K physical rows and 4 K physical columns, having 64 cells per bitline segment), for instance, the number of primary SA/WD circuits required to be disposed on global I/O lines increases to 64. Even this arrangement is not effective because of lack of drive as well as rapid buildup of diode capacitance on the global I/O lines due to frequent primary SA circuits.
Increasing the number of cells per bitline segment (which can increase the speed on the global path by reducing the number of sense amp stripes, reducing the amount of parasitic diode capacitance on the global path) also does not solve the problem because it creates a significant speed penalty for normal bitlines used in memories, particularly for dynamic random access memory (DRAM) structures. Static RAM (SRAM) structures are also negatively impacted by this drawback. In addition, this approach is beset with a significant write power penalty as well, due to full swing voltages on longer differential bitlines, as compared to differential or power-reduced single-ended swings on global I/O lines.
SUMMARY OF THE INVENTION
Accordingly, the present invention advantageously provides a hierarchical sense amp and write driver (SA/WD) circuitry architecture for compilable high-density memory that optimizes speed, power, and area considerations. A predetermined number of secondary, or regional, SA/WD blocks segment the main array associated with the memory instance in multiple banks. Each secondary SA/WD block is coupled to a tertiary, or global, SA/WD block via a global I/O line operable to effectuate data I/O with respect to the memory instance. A select number of primary SA/WD blocks per each secondary SA/WD block are specified, wherein the primary SA/WD blocks segment a memory bank associated with the particular secondary SA/WD block into a plurality of sub-banks. Each primary SA/WD block is coupled to a select secondary SA/WD block associated therewith via a regional I/O line. A select number of memory cells per bitline segment driven by the primary SA/WD block (having absolute minimum geometry, e.g., cross-coupled latch used for reading and writing, with pass gates only) for each of the memory sub-banks may be specified as part of compiling a memory instance for a particular application.
In one exemplary embodiment, the memory instance comprises a multi-bank DRAM array wherein circuitry comprising the regional SA/WD block(s) may preferably be provided as a plurality of conventional single-ended buffer stages (typically comprised of standard CMOS inverters) applied in both directions (one for the Data In path and the other for the separate Data Out path). Also, the regional SA/WD circuitry may preferably be comprised of bi-directional small signal transceiver/repeater circuitry that allows differential read as well as write capability.
In another exemplary embodiment, the memory instance comprises a multi-bank SRAM array having one or more regional SA/WD blocks with circuitry such as described in
Mai Son
Smith ,Danamraj & Youst, P.C.
Virage Logic Corp.
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