Hierarchical scan architecture for design for test applications

Details Hierarchical scan architecture for design for test applications Hierarchical scan architecture for design for test applications

1996-08-28

1999-09-07

Teska, Kevin J.

Boots, shoes, and leggings

364578, 371 2231, G06F 1750, G01R 3128

Patent

active

059496924

ABSTRACT:
A system and method for architecting design for test circuitry (e.g., scan architecting) within an integrated circuit design having subdesigns (e.g., modules). The novel system contains a default operational mode (no user specification) and an operational mode based on user specifications; within either mode, the system recognizes and allows definition of subdesign scan chains which can be linked together alone or with other scan elements to architect complex scan chains (e.g., top level scan chains). The system includes specification, analysis, synthesis and reporting processes which can be used in an IC design having a hierarchical structure including modules. The specification process accesses a design database and a script file and allows a user to define global scan properties (scan style, number of chains, etc.), properties of a particular scan chain (membership, name, etc.), test signals (scan-in, scan-out, scan-enable, etc.), complex elements used as part of a scan chain without requiring scan replacement, wires and latches forming connections between scan elements; this information is associated with the selected design database. Analysis reads the design database and performs architecting of scan chains based on inferred scan elements of the design and defined (e.g. specified) scan elements. During analysis, the logic within the design database is not altered and a script is generated for user modification/verification. Specification and analysis can be executed iteratively until the desired scan structures are planned. Synthesis then implements the desired DFT circuitry by altering the design database based on the scan chains planned by analysis.

REFERENCES:
patent: 4947357 (1990-08-01), Stewart et al.
patent: 5497378 (1996-03-01), Amini et al.
patent: 5617430 (1997-04-01), Angelotti et al.
patent: 5627842 (1997-05-01), Brown et al.
patent: 5638380 (1997-06-01), De
patent: 5661733 (1997-08-01), Schoessow
patent: 5696771 (1997-12-01), Beausang et al.
patent: 5703789 (1997-12-01), Beausang et al.
patent: 5717702 (1998-02-01), Stokes et al.

Affiliated with

Also associated with

Rating

Hierarchical scan architecture for design for test applications does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Hierarchical scan architecture for design for test applications, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Hierarchical scan architecture for design for test applications will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1810789