Hierarchical priority branch handling for parallel execution in

Boots – shoes – and leggings

Patent

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

G06F 928, G06F 942

Patent

active

048335991

ABSTRACT:
In a parallel data processing system having a plurality of separately operating arithmetic processing units, a method and apparatus allows a plurality of branch instructions to be operated upon in a single machine cycle. The branch instructions have associated therewith a hierarchical priority system and the method and apparatus determine which branch, if any, should be taken. In particular, the method and apparatus simultaneously determine, during the parallel execution of the branch instructions, whether any branch test condition associated with a branch instruction is true, and independently, the target address for each branch instruction and a fall-through instruction address if a branch instruction is not taken.

REFERENCES:
patent: 3611306 (1971-10-01), Reigel et al.
patent: 4199811 (1980-04-01), Borgerson et al.
patent: 4223379 (1980-09-01), Simcoe
patent: 4307447 (1981-12-01), Provanzano et al.
patent: 4435758 (1984-03-01), Lorie et al.
patent: 4446518 (1984-05-01), Casamatta
patent: 4484303 (1984-11-01), Provanzano et al.
patent: 4571673 (1986-02-01), Horst et al.
patent: 4594659 (1986-06-01), Guenthner et al.
patent: 4616313 (1986-10-01), Aoyagi
patent: 4633390 (1986-11-01), Yoshida
Fisher, "The VLIW Machine: a Multiprocessor for Compiling Scientific Code", Computer, Jul. 1984, pp. 45-53.
Fisher et al., "Parallel Processing: A Smart Compiler and a Dumb Machine", Dept. of Computer Science, Yale University.
Riseman et al., "The Inhibition of Potential Parallelism by Conditional Jumps", IEEE Transactions on Computers, Dec. 1972, Short Notes, pp. 1405-1415.
Fisher et al., "VLIW Machines: Multiprocessors We Can Actually Program", Dept. of Computer Science, Yale University.
Tjaden et al., "Detection and Parallel Execution of Independent Instructions", IEEE Transactions on Computers, vol. C-19, No. 10, Oct. 1970, pp. 889-895.
Hack, "Peak vs. Sustained Performance in Highly Concurrent Vector Machines", Computer, Sep. 1986, pp. 11-19.
Amdahl, "Validity of the Single Processor Approach to Achieving Large Scale Computing Capabilities", Spring Joint Computer Conf., 1967, pp. 483-485.
Fisher, "The Optimization of Horizontal Microcode Within and Beyond Basic Blocks: An Application of Processor Scheduling with Resources", U.S. Department of Energy Report, Mathematics and Computing, COO-3077-161.

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

Hierarchical priority branch handling for parallel execution in does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Hierarchical priority branch handling for parallel execution in , we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Hierarchical priority branch handling for parallel execution in will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-1734863

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.