Hierarchical prefetch for semiconductor memories

Details Hierarchical prefetch for semiconductor memories Hierarchical prefetch for semiconductor memories

1999-06-15

2000-06-27

Elms, Richard

Static information storage and retrieval

Addressing

Sync/clocking

365220, 365221, G11C 800

Patent

active

060814799

ABSTRACT:
A semiconductor memory in accordance with the present invention includes a data path including a plurality of hierarchical stages, each stage including a bit data rate which is different from the other stages. At least two prefetch circuits are disposed between the stages. The at least two prefetch circuits include at least two latches for receiving data bits and storing the data bits until a next stage in the hierarchy is capable of receiving the data bits. The at least two prefetch circuits are coupled between stages such that an overall data rate per stage between stages are substantially equal. Control signals control the at least two latches such that prefetch circuits maintain the overall data rate between the stages.

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