Television – Camera – system and detail – Solid-state image sensor
Reexamination Certificate
2000-04-20
2004-08-31
Le, Vu (Department: 2612)
Television
Camera, system and detail
Solid-state image sensor
C250S208100
Reexamination Certificate
active
06784932
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to solid-state imaging devices, and more particularly to a hierarchical pixel readout multiplexer for serially reading charges column by column from each row of a matrix array of sensors, or pixels.
2. Description of the Related Art
In a solid-state imaging device, photodiode sensors (pixels) are arranged in a matrix array of rows and columns (FIG.
1
). A large number of row select transistors are connected to each column select line to respond to row select signals from a row scanner
11
for simultaneously developing charges from the photodiodes of each row. The developed charges are then serially read out from the column select lines into an external circuit. Since many row select transistors are connected to each column select line, the latter is over-loaded by parasitic capacitances and hence it is not sufficient for a single buffer to drive the external circuit at high speed. To solve this problem, the capacitive load of each column select line is distributed among a number of buffers, as disclosed in “A 200 mW 3.3V CMOS Color Camera IC chip Producing 352×288 24
b
Video at 30 Frames/s”, M. Loniaz et al., (The 1998 IEEE International Sold Solid-State Circuits Conference Digest of Technical Papers, pp. 168-169). One example of such pixel readout multiplexer
12
is shown in
FIG. 1
as comprising a plurality of buffers (unity-gain amplifiers)
14
,
15
and
16
connected in stages of hierarchical configuration, with the first-stage buffers
14
being connected respectively to the column select lines of the matrix array
10
and divided into groups corresponding to the second-stage buffers
15
. The output of each first-stage buffer
14
is connected by a switch
17
to the associated second-stage buffer
15
, whose output is connected by a switch
18
to the input of the third-stage buffer
16
. Switches
17
and
18
are controlled by a column scanner
13
so that each column select line is successively connected through the associated first- and second-stage buffers
14
and
15
to the third-stage buffer
16
.
However, since different buffers are used to read signals from the column select lines, variability of their operating characteristics, such as voltage offsets, results in an output signal which deviates from what would otherwise be produced by an ideal single buffer. For example, if two first-stage buffers have uniquely different offset voltages, the output of each buffer would deviate from the input voltage by an amount corresponding to its own offset voltage. If the input signals of such buffers are of equal magnitude, the difference between their offset voltages results in the generation of noise in the output signal.
SUMMARY OF THE INVENTION
It is therefore an object of the present invention to provide a hierarchical readout circuit that can compensate for buffer offsets.
According to a first aspect of the present invention, there is provided a hierarchical readout circuit comprising a plurality of first capacitors respectively interposed in a plurality of lines at which individual voltages are developed, a plurality of first buffers respectively connected to the outputs of the first capacitors, scanning circuitry for selectively coupling one of the outputs of the first buffers to a circuit node, a second buffer for producing an output signal, and a second capacitor connected between the circuit node and the second buffer. Bias control circuitry is provided for controlling potentials at the inputs and the outputs of the first capacitors and a potential at the output of the second capacitor so that the output signal of the second buffer contains a differential voltage between a bias voltage and each of the individual voltages.
In a preferred embodiment, the control circuitry is configured to simultaneously bias the inputs and outputs of the first capacitors before the individual voltages appear at the lines, selectively bias the output of each of the first capacitors again in the presence of the individual voltages at the lines, and periodically bias the output of the second capacitor before each of the first capacitors is selectively biased again.
According to a second aspect, the present invention provides a hierarchical readout circuit comprising a plurality of first capacitors for respectively interposed in a plurality of lines at which individual voltages are developed, first voltage biasing circuitry for simultaneously biasing the inputs of the first capacitors at least once before the individual voltages appear at the plurality of lines, second voltage biasing circuitry for simultaneously biasing the outputs of the first capacitors before the individual voltages appear at the lines and selectively biasing the output of each of the first capacitors again in the presence of the individual voltages at the lines, a plurality of first buffers respectively connected to the outputs of the first capacitors, scanning circuitry for selectively coupling the output of each of the first buffers to a circuit node, a second buffer for producing an output signal, a second capacitor connected between the circuit node and the second buffer, and third voltage biasing circuitry for biasing the output of the second capacitor before the individual voltages appear at the lines and at periodic intervals before each of the first capacitors is selectively biased again by the second biasing circuitry.
REFERENCES:
patent: 5144133 (1992-09-01), Dudley et al.
patent: 5296696 (1994-03-01), Uno
patent: 5485206 (1996-01-01), Nakagawa et al.
patent: 6476864 (2002-11-01), Borg et al.
patent: 2001/0012070 (2001-08-01), Enod et al.
patent: 2000-077642 (2000-03-01), None
patent: 2000-115642 (2000-04-01), None
“A 200 mW 3.3V CMOS Color Camera IC Producing 352x288 24b Video at 30 Frames/s”; M. Loinaz et al.; pp. 168-169.
Jerabek Kelly L.
Katten Muchin Zavis & Rosenman
Le Vu
NEC Corporation
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