Hierarchical pattern faults for describing logic circuit failure

Details Hierarchical pattern faults for describing logic circuit failure Hierarchical pattern faults for describing logic circuit failure

1994-06-09

1996-08-13

Voeltz, Emanuel T.

Excavating

371 221, 364578, G06F 11263, G01R 313183

Patent

active

055464084

ABSTRACT:
A method and system (12) for defining and using a pattern fault file (15) having a static pattern fault and/or a dynamic pattern fault. A static pattern fault is represented as a list of required excitation nodes and their values, as well as a fault propagation point. The fault propagation point is defined to be a net or node in a circuit to be tested where the defect's effect first appears once it has been excited. A dynamic pattern fault adds to this structure an initial value list of nodes and their required initial values. The dynamic-pattern fault is employed to advantage when a two pattern sequence is required to excite a specific defect. Logical combinations (AND/OR) of specified pin excitations and fault propagation points may be employed. The excitation value list, the initial value list and the propagation point can include any of the following: input pins of an entity; output pins of the entity; nets inside of the entity; pins on usage blocks inside the entity; nets inside a usage of a lower entity; and pins inside a usage of a lower level entity. The method and system also provide a capability to define pattern faults for each entity in a hierarchial circuit definition, and thus provides a mechanism to define pattern faults for specific cells in a cell technical library (13).

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IBM Technical Disclosure Bulletin, vol. 31 No. 2, Jul. 1988-Flexible Fault Model for Test Generation-pp. 299-302.

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