Hierarchical parallel pipelined operation of analog and...

Details Hierarchical parallel pipelined operation of analog and... Hierarchical parallel pipelined operation of analog and...

2006-03-14

2006-03-14

Le, Don (Department: 2819)

Coded data generation or conversion

Analog to or from digital conversion

Analog to digital conversion

C341S159000, C341S158000

Reexamination Certificate

active

07012559

ABSTRACT:
A hierarchical parallel pipelined circuit includes a first stage with a plurality of sampling circuits and a plurality of corresponding analog or digital circuits that receive an output from the plurality of sampling circuits. A second stage includes a second plurality of sampling circuits and a plurality of corresponding analog or digital circuits that receive an output from the plurality of sampling circuits. A multi-frequency, multi-phase clock clocks the first and second stages, the multi-frequency, multi-phase clock providing a first clock having a first frequency having either a single or plurality of phases, and a second clock having a second frequency having a plurality of phases. A first phase of a plurality of phases is phase locked to the first phase of the first clock. The clock frequency multiplied by the number of parallel devices in each stage is the throughput of the circuit and is kept constant across the stages.

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Poulton, Ken et al., A 20GS/s 8b ADC with a 1MB Memory in 0.18μm CMOS, 2003 IEEE International Solid-State Circuits Conference, ISSCC 2003 / Session 18/NYQUIST A/D Converters / Paper 18/1, 10 pp., no month.

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