Hierarchical method of power supply noise and signal...

Data processing: structural design – modeling – simulation – and em – Simulating electronic device or electrical system – Circuit simulation

Reexamination Certificate

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C703S002000, C716S030000, C716S030000, C716S030000

Reexamination Certificate

active

10711168

ABSTRACT:
The invention relates generally to a method of power supply noise and signal integrity analysis for creating frequency-dependent electrical models particularly related to microelectronic packages. The method discloses creation of equivalent circuits for geometries encountered in a typical chip package, including how to partition the geometry into cells which are less then 1/20 the minimum wavelength (λ) in size, and how to handle signal and power supply vias, signal wires, and power planes. The method also instructs how to assign values to each of the inductors, capacitors, resistors, and transmission lines in each equivalent circuit. The method further provides modeling of only those interactions which occur between adjacent cells.

REFERENCES:
patent: 6584596 (2003-06-01), Buffet et al.
patent: 2003/0061571 (2003-03-01), Buffet et al.
Shumakher et al., E. On the Noise Properties of Injection-Locked Oscillators, IEEE Transactions on Microwave Theory and Techniques, vol. 52, No. 5, May 2004, pp. 1523-1537.
Rosenbaum et al., E. Silicon Dioxide Breakdown Lifetime Enhancement Under Bipolar Bias Conditions, IEEE Transaction on Electron Devices, vol. 40 No. 12, Dec. 1993, pp. 2287-2295.
Kust et al., E. Influence of Solvent Nature on the Elctrochemical Parameters of Electrical Double Layer Capacitors, Journal of Electroanalytical Chemistry, vol. 562, No. 1, Jan. 2004, pp. 33-42.
Van Heijningen et al., High-Level Simulation of Substrate Noise Generation including Power Supply Noise Coupling, Proceedings of the 37thConference on Design Automation, Jun. 2000, ACM Press, pp. 446-451.

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