Hierarchical memory system with logical cache, physical cache, a

Details Hierarchical memory system with logical cache, physical cache, a Hierarchical memory system with logical cache, physical cache, a

1988-04-12

1990-05-15

Lee, Thomas C.

Boots, shoes, and leggings

36423221, 36424341, 36424345, 3642511, 364736, G06F 1210, G06F 1516

Patent

active

049263170

ABSTRACT:
A vector processing computer (20) includes a memory control unit (22), main memory (99), a central processor (156), a service processing unit (42) and a plurality of input/output processors (54, 68). The central processor (156) includes a physical cache unit (100), an address translation unit (118), an instruction processing unit (126), an address scalar unit (142), a vector control unit (144), an odd pipe vector processing unit (148) and an even pipe vector processing unit (150). Vector elements are transmitted from memory, either main memory (99), a physical cache unit (100) or a logical cache (326) through a source bus (114) where the elements are alternately loaded into the vector processing units (148, 150). The resulting vectors are transmitted through a destination bus (114) to either the physical cache unit (100), the main memory (99), the logical cache (326) or to an input/output processor (54). In a still further aspect of the computer (20) there is included the logical data cache (326) which stores data at logical addresses such that the central processor (156) can store and retrieve data without the necessity of first making a translation from logical to physical address.

REFERENCES:
patent: 4020466 (1977-04-01), Cordi et al.
patent: 4128880 (1978-12-01), Cray, Jr.
patent: 4464712 (1984-08-01), Fletcher
patent: 4481573 (1984-11-01), Fukunaga et al.
patent: 4495575 (1985-01-01), Eguchi
patent: 4533995 (1985-08-01), Christian et al.
patent: 4550367 (1985-10-01), Hattori et al.
patent: 4569018 (1986-02-01), Hummel et al.
patent: 4594682 (1986-06-01), Drimak
patent: 4669043 (1987-05-01), Kaplinsky
patent: 4682281 (1987-07-01), Woffinden et al.
"Encyclopedia of Computer Science and Engineering", 2nd Edition, Van Nostrand Reinhold Company, 1983, pp. 195-196.
Nissen, S. M. & Wallach, S. J., "The All Applications Digital Computer", ACM-IEEE Symposium on High-Level-Language Computer Architecture, Nov. 7 & 8, 1973.
Kogge, P. M., The Architecture of Pipelined Computers, 1981, Chaps. 2, 4 and 6.
Lorin, H., Parallelism in Hardware and Software: Real and Apparent Concurrency, 1972, Chap. 8.

Affiliated with

Also associated with

Rating

Hierarchical memory system with logical cache, physical cache, a does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Hierarchical memory system with logical cache, physical cache, a, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Hierarchical memory system with logical cache, physical cache, a will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-626283