Hierarchical memory system for microcode and means for correctin

Details Hierarchical memory system for microcode and means for correctin Hierarchical memory system for microcode and means for correctin

1993-10-06

1999-04-27

Lall, Parshotam S.

395568, 395595, G06F 924

Patent

active

058988670

ABSTRACT:
A multiprocessor computer system includes a system clock, a main memory connected through a memory bus to a microinstruction memory and a microinstruction decoder. Circuitry detects whether the microinstruction being decoded is the wrong microinstruction or has a parity error. On detection of such an erroneous microinstruction, the microinstruction is reloaded from the main memory into the microinstruction memory and then passed to the microinstruction decoder without interrupting the system clock or operation of the other processors.

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