Static information storage and retrieval – Addressing – Plural blocks or banks
Patent
1996-06-11
1998-03-31
Fears, Terrell W.
Static information storage and retrieval
Addressing
Plural blocks or banks
36523001, G11C 1300
Patent
active
057346208
ABSTRACT:
An integrated memory array circuit, such as a DRAM, has a global bit line communicating a global bit line signal with a first electrode of each of a plurality of FET devices. The primary global bit line has a plurality of subarray bit lines. Each subarray bit line communicates a subarray bit line signal with a second electrode of one of the FET devices and with a first electrode of each of a plurality of subarray FET devices. Each subarray FET device has a gate communicating a word line signal with a word line. Each subarray FET device has a second electrode communicating a one bit storage signal with a capacitor. Each subarray FET is activated by a word line signal from a corresponding word line to electrically isolate a corresponding capacitor from its corresponding subarray bit line, or to electrically connect the corresponding capacitor with its corresponding subarray bit line. A device senses and amplifies the global bit line signal and outputs an amplified global bit line signal to a column decode device. A redundancy logic controller implements both row and column redundancy for replacement of defective memory array components by redundant components included in the memory array structure, including redundant global bit line, subarray bit lines, FETs, word lines, and capacitors.
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Fears Terrell W.
Micro)n Technology, Inc.
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