Hierarchical memories having two ports at each subordinate memor

Details Hierarchical memories having two ports at each subordinate memor Hierarchical memories having two ports at each subordinate memor

1982-08-06

1984-12-18

Zache, Raulfe B.

Boots, shoes, and leggings

G06F 1300

Patent

active

044893817

ABSTRACT:
A hierarchical memory system is disclosed comprising at least one dual-ported memory level, each port having access to a separate bidirectional data bus. The port facing the higher memory levels is equipped with a pair of data buffers having a bit width equal to the bit width of a single row of cells in the storage array contained within the dual-ported level. One buffer (output) is loaded in one cycle from the array. The outer buffer (input) is emptied in one cycle into the array. Both buffers interact with the higher memory level independently of the transferring of data through the other of the dual ports. Thus, contention for the use of bus facilities and contention for memory cycles are greatly reduced in the transferring of data between the memory levels.

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IBM Technical Disclosure Bulletin, vol. 23, No. 7A, Dec. 1980, "Multi-Port Asymmetrical Memory Cell", R. C. Joy and E. Seewann, p. 2822.

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