Boots – shoes – and leggings
Patent
1995-06-21
1996-04-30
Trans, Vincent N.
Boots, shoes, and leggings
364490, G06F 1750
Patent
active
055131190
ABSTRACT:
A set of logic cells is hierarchically grouped to form groups to be placed on an integrated circuit for gate array layout. A user interface allows a user to interact with a placement system. The system is supplied with input design files defining the integrated circuit, the cells to be grouped, the groups to be placed, and input/output buffers to be placed on the perimeter of the integrated circuit for connecting the groups with external circuitry. The system reads the input design files to create a database used for placing desired input/output buffers and for hierarchically grouping the cells and placing the groups. The groups are defined by their size, determined using utilization and aspect ratio values of the areas where the cells are to be placed. The user is allowed to move the buffers and groups to any valid locations within the integrated circuit.
REFERENCES:
patent: 3603771 (1971-09-01), Isett et al.
patent: 3654615 (1972-04-01), Freitag
patent: 5191542 (1993-03-01), Murofushi
"A Procedure for Placement of Standard-Cell VLSI Circuits" by Dunlop et al., IEEE Transactions on Computer-Aided Design, vol. CAD-4, No. 1, Jan. 1985, pp. 92-98.
"Circuit Layout" by J. Soukup, IEEE Proceeding, vol. 69, Oct. 1981, pp. 21-44.
Huffman Ward
Moore Wesley
Mitsubishi Semiconductor America Inc.
Trans Vincent N.
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