Hierarchical encoder including timing and data detection devices

Details Hierarchical encoder including timing and data detection devices Hierarchical encoder including timing and data detection devices

1997-08-12

1999-12-07

Tran, Andrew Q.

Static information storage and retrieval

Associative memories

Ferroelectric cell

36523003, 36518912, 36518905, G11C 1504

Patent

active

059994347

ABSTRACT:
An associative memory to which an encoder is applied has a plurality of associative memory subblocks each having a plurality of memory words. A hit flag resulting from match retrieval of retrieval data and the contents of the memory word, and an empty flag indicating whether or not the contents of the memory word are valid as objects for match retrieval are output from each memory word of each associative memory subblock. The address of an invalid memory word is readily controllable since the address of the memory word corresponding to the empty flag can be output as in a case where the address of the memory word corresponding to the hit flag is output. Moreover, since the hit flag and the empty flag are allowed to share a detection line with each other for common use in this encoder, the layout area of the associative memory is reduced and it is possible to build up a high-density associative memory.

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