Electrical computers and digital processing systems: multicomput – Computer-to-computer protocol implementing – Computer-to-computer data transfer regulating
Reexamination Certificate
1999-07-22
2004-04-13
An, Meng-Al T. (Department: 2756)
Electrical computers and digital processing systems: multicomput
Computer-to-computer protocol implementing
Computer-to-computer data transfer regulating
C709S234000, C709S235000, C370S395400, C370S395700, C370S412000, C370S413000, C370S415000, C370S417000
Reexamination Certificate
active
06721796
ABSTRACT:
FIELD OF INVENTION
Invention relates to electronic storage, particularly to hierarchical buffer systems.
BACKGROUND OF INVENTION
Conventional digital electronics systems employ various storage structures, including buffers, queues, caches, or other similar memory devices. More recently, especially for distributed networking and applications, such as those applications for enabling high-speed transmission, processing, and storage of so-called Internet or related digital data or signaling traffic, buffers and similar electronic repositories are increasingly used as temporary storage, for example, to avoid or otherwise manage congestion of traffic flow of packets, cells, frames or other data units through a network gateway.
Various approaches are used to police gateway queuing of traffic load at given times. In particular, with buffer structures being used to hold temporary excess traffic load at a gateway, numerous buffer management algorithms are proposed, such as last packet discard (i.e., “drop tail” approach), randomization (i.e., “early random drop” (ERD), “random early detection” (RED), “flow random early drop” (FRED)), as discussed in further detail in references cited in this patent application, which are hereby incorporated by reference as appropriate.
However, such present approaches are limited in optimizing data throughput and maintaining fairness amongst different flows, particularly for processing arriving data units for allocation in hierarchical buffer systems. Accordingly, an improved solution is required to optimize data throughput and storage.
SUMMARY OF INVENTION
Invention resides in a multi-level buffer system and/or method for managing buffer resources to reduce or eliminate network congestion, particularly by dynamically allocating storage resources to arriving data units according to hierarchical acceptance criteria. Moreover, stored data units are retrievable according to hierarchical schedule.
Acceptance criteria may comprise minimum and/or maximum threshold values, which are pre-specified or dynamically computed, and may be determined from system resource and storage availability. Data units are accepted for allocated buffer storage upon dynamically-determined satisfaction of certain hierarchically-based acceptance criteria. Such criteria may be determined from reserved minimum buffer length, calculated maximum buffer length, or random early discard-type algorithm applied separately to each buffer level.
REFERENCES:
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patent: 6018527 (2000-01-01), Yin et al.
patent: 6219728 (2001-04-01), Yin
patent: 6249359 (2001-06-01), Aoki et al.
“Circular Dat Buffers with Fast Bypass Path,” IBM Technical Disclosure Bulletin, vol. 37, pp. 15-16, Apr. 1, 1994.*
“Ram-Based Packet Switch With Overflow Buffers,” IBM Technical Disclosure Bulletin, vol. 32, pp. 308-310, Jan. 1, 1990.*
Floyd, Sally and Jacobson, Van. Random Early Detection Gateways for Congestion Avoidance. IEEE/ACM Transactions on networking, Aug. 1993.
Lin, Dong and Morris, Robert. Dynamics of Random Early Detection SIGcom. 1997, pp. 1-11.
Choudhury, Abhijit K. and Hahne, Ellen L. Dynamic Queue Length Thresholds in a Shared Memory ATM Switch. IEEE, 1996, (679-687 pgs.).
An Meng-Al T.
Campbell Stephenson Ascolese LLP
Cisco Technology Inc.
Hu Jinsong
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