Hierarchical DRAM array with grouped I/O lines and high speed se

Details Hierarchical DRAM array with grouped I/O lines and high speed se Hierarchical DRAM array with grouped I/O lines and high speed se

1994-04-04

1997-06-10

Gossage, Glenn

Static information storage and retrieval

Interconnection arrangements

365 51, 36518905, 36518907, 365203, 365205, G11C 506, G11C 502, G11C 700, G11C 1140

Patent

active

056383177

ABSTRACT:
A random access memory array architecture including a plurality of arrays or subarrays arranged into rows and columns, a plurality of sense amplifiers between the arrays (2), and grouped input/output (I/O) lines. The I/O path includes main I/O lines (24) coupled to all of the arrays, with orthogonal local I/O lines (20) for a column of arrays plus sub I/O lines (16) orthogonal to the local I/O lines for each group of sense amplifiers in a row of sense amplifiers. A plurality of pass transistor pairs and interconnect transistors are coupled to the sense amplifiers and the local and sub I/O lines. Latches are provided for storing data output from each of the subarrays, and a match comparator is connected to at least two of the latches for providing a signal on a complementary pair of match leads indicative of a comparison of the data in the latches. A true lead of the complementary pair of match leads is precharged high before the comparison while a complement lead of the complementary pair of match leads is precharged low.

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