Static information storage and retrieval – Addressing – Particular decoder or driver circuit
Reexamination Certificate
2007-10-22
2009-12-15
Tran, Michael T (Department: 2827)
Static information storage and retrieval
Addressing
Particular decoder or driver circuit
C365S230030
Reexamination Certificate
active
07633829
ABSTRACT:
A memory array comprising array lines of first and second types coupled to memory cells includes a first hierarchical decoder circuit for decoding address information and selecting one or more array lines of the first type. The first hierarchical decoder circuit includes at least two hierarchical levels of multi-headed decoder circuits. The first hierarchical decoder circuit may include a first-level decoder circuit for decoding a plurality of address signal inputs and generating a plurality of first-level decoded outputs, a plurality of second-level multi-headed decoder circuits, each respective one coupled to a respective first-level decoded output, each for providing a respective plurality of second-level decoded outputs, and a plurality of third-level multi-headed decoder circuits, each respective one coupled to a respective second-level decoded output, each for providing a respective plurality of third-level decoded outputs coupled to the memory array.
REFERENCES:
patent: 3154636 (1964-10-01), Schwertz
patent: 4646266 (1987-02-01), Ovshinsky et al.
patent: 5250859 (1993-10-01), Kaplinsky
patent: 5285118 (1994-02-01), Montegari
patent: 5751012 (1998-05-01), Wolstenholme et al.
patent: 5835396 (1998-11-01), Zhang
patent: 5963500 (1999-10-01), Taura et al.
patent: 6034882 (2000-03-01), Johnson et al.
patent: 6055180 (2000-04-01), Gudesen et al.
patent: 6185121 (2001-02-01), O'Neill
patent: 6185122 (2001-02-01), Johnson et al.
patent: 6191999 (2001-02-01), Fujieda et al.
patent: 6363000 (2002-03-01), Perner et al.
patent: 6407953 (2002-06-01), Cleeves
patent: 6420215 (2002-07-01), Knall et al.
patent: 6522594 (2003-02-01), Scheuerlein
patent: 6545898 (2003-04-01), Scheuerlein
patent: 6567287 (2003-05-01), Scheuerlein
patent: 6584034 (2003-06-01), Hsu et al.
patent: 6591394 (2003-07-01), Lee et al.
patent: 6618295 (2003-09-01), Scheuerlein
patent: 6631085 (2003-10-01), Kleveland et al.
patent: 6735104 (2004-05-01), Scheuerlein
patent: 6754746 (2004-06-01), Leung et al.
patent: 6768685 (2004-07-01), Scheuerlein
patent: 6856572 (2005-02-01), Scheuerlein et al.
patent: 6859410 (2005-02-01), Scheuerlein et al.
patent: 6876569 (2005-04-01), Itoh et al.
patent: 6879505 (2005-04-01), Scheuerlein
patent: 6888750 (2005-05-01), Walker et al.
patent: 6901006 (2005-05-01), Kobayashi et al.
patent: 7002825 (2006-02-01), Scheuerlein
patent: 7023739 (2006-04-01), Chen et al.
patent: 7106652 (2006-09-01), Scheuerlein
patent: 7177169 (2007-02-01), Scheuerlein
patent: 7177183 (2007-02-01), Scheuerlein et al.
patent: 7221588 (2007-05-01), Fasoli et al.
patent: 7286439 (2007-10-01), Fasoli et al.
patent: 7298665 (2007-11-01), So et al.
patent: 7307268 (2007-12-01), Scheuerlein
patent: 2002/0028541 (2002-03-01), Lee et al.
patent: 2003/0021148 (2003-01-01), Scheuerlein
patent: 2003/0128581 (2003-07-01), Scheuerlein et al.
patent: 2003/0202406 (2003-10-01), Issa
patent: 2003/0214841 (2003-11-01), Scheuerlein et al.
patent: 2004/0100831 (2004-05-01), Knall et al.
patent: 2004/0124466 (2004-07-01), Walker et al.
patent: 2004/0125629 (2004-07-01), Scheuerlein et al.
patent: 2004/0145024 (2004-07-01), Chen et al.
patent: 2004/0190360 (2004-09-01), Scheuerlein
patent: 2005/0128807 (2005-06-01), Chen et al.
patent: 2005/0226049 (2005-10-01), Jeong et al.
patent: 2006/0120200 (2006-06-01), Pochmuller
Naji, Petet K., et al., “A 256kb 3.0V 1T1MTJ Nonvolatile Magnetoresistive RAM,” 2001 IEEE ISSCC, Feb. 6, 2001, Paper 7.6, and associated slide handouts, 35 pages.
Kenneth K. So, Luca G. Fasoli; and Roy E. Scheuerlein, U.S. Appl. No. 11/026,493, filed Dec. 30, 2004.
Compardo, Giovanni, et al., “40-mm.sup.2 3-V-Only 50-MHz 65-Mb 2-b/cell CHE NOR Flash Memory,” IEEE Journal of Solid-State Circuits, vol. 35, No. 11, Nov. 2000, pp. 1655-1667.
Motta, Ilaria, et al., “High-Voltage Management in Single-Supply CHE NOR-Type Flash Memories,” Proceedings of the IEEE, vol. 91, No. 4, Apr. 2003, pp. 554-568.
Okuda, Takashi and Murotani, Tatsunori, “A Four-Level Storage 4-Gb DRAM,” IEEE Journal of Solid-State Circuits, vol. 32, No. 11, Nov. 1997, pp. 1743-1747.
European Search Report mailed Oct. 14, 2008 for EP App. No. 05854312.5, 6 pages.
Fasoli Luca G.
So Kenneth K.
SanDisk 3D LLC
Tran Michael T
Zagorin O'Brien Graham LLP
LandOfFree
Hierarchical decoding of dense memory arrays using multiple... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Hierarchical decoding of dense memory arrays using multiple..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Hierarchical decoding of dense memory arrays using multiple... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-4144638