Hierarchical column select line architecture for multi-bank DRAM

Details Hierarchical column select line architecture for multi-bank DRAM Hierarchical column select line architecture for multi-bank DRAM

1997-09-11

1998-10-13

Nelms, David

Static information storage and retrieval

Addressing

Plural blocks or banks

36523006, 365 63, G11C 800

Patent

active

058222685

ABSTRACT:
A multi-bank DRAM having a hierarchical column select line architecture is described. The DRAM is provided with a plurality of memory cells which are organized in at least two banks. Each of the banks includes memory cells which are arranged in rows and columns. The memory cells store data provided by at least one bit line and at least one data line. The DRAM includes: a first switch for selecting one of the two banks; and a second switch connected to the first switch for selecting one of the columns, wherein the first and second switches couple one of the bit lines to one of the data lines, enabling data to be written into or read out of memory cells common to the selected bank and to the selected column. The first switch is controlled by a plurality of bank CSLs (BCSLs), wherein the BCSLs are shared by some of the blocks within the same bank, but not by any of the blocks in other banks. The second switch is controlled by a plurality of global CSLs (GCSLs), the GCSLs being shared by all remaining banks within a unit. The BCSLs and GCSLs are controlled by the bank column decoder and by the global column decoder.

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Y. Watanabe, et al, "A 286 mm.sup.2 256 Mb DRAM with .times.32 Both-Ends DQ" IEEE Journal of Solid-State Circuits, V. 31, #4, Apr. 1996, pp. 567-574.
T. Saeki, et al, "A 2.5-ns Clock Access, 250-MHz, 256-Mb SDRAM with Synchronous Mirror Delay" IEEE Journal of Solid-State Circuits, V. 31, #11, Nov. 1996, pp. 1656-1668.
Jei-Hwan Yoo, et al, "A 32-Bank 1 Gb Self-Strobing Synchronous DRAM with 1 GByte/s Bandwidth" IEEE Journal of Solid-State Circuits, V. 31, #11, Nov. 1996, pp. 1635-1644.

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