Hierarchical clock grid for on-die salphasic clocking

Details Hierarchical clock grid for on-die salphasic clocking Hierarchical clock grid for on-die salphasic clocking

2001-06-27

2003-02-18

Callahan, Timothy P. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Clock or pulse waveform generating

C327S293000, C327S297000

Reexamination Certificate

active

06522186

ABSTRACT:

FIELD OF THE INVENTION
The invention relates generally to microelectronic circuits and, more particularly, to clock distribution structures for use therein.
BACKGROUND OF THE INVENTION
Clock distribution has become a major on-chip performance bottleneck within microprocessors and other integrated circuits (ICs). As clock frequencies increase, proportionately lower clock skews are required. At the same time, clock interconnects begin to behave more like transmission lines than simple resistance-capacitance (RC) networks. For conventional clock grids and trees, which seek to remain in the RC domain, two options for supporting increased clock speeds include: (a) increasing the resistance and capacitance of the clock lines relative to inductance of the lines, and (b) reducing the interconnect length between buffers within the clock network. Neither of these approaches, however, can provide the performance increases that will be required by integrated circuits of the future. For example, an increase in line capacitance will typically require an increase in power. As ICs become smaller, however, on-die heat dissipation becomes a bigger problem and lower power circuit techniques are desired. Also, an increase in either resistance or capacitance will increase the time constant of the circuit, which increases skew. Similarly, a reduction in interconnect length between buffers will require the insertion of additional buffers into the clock network, which will increase power consumption and typically result in additional clock jitter and skew.
Salphasic clocking is a technique that makes use of standing waves to achieve low clock skew within a system. Salphasic clocking techniques also typically consume substantially less power than other known clocking strategies. In the past, it has been difficult to implement salphasic clocking on-die within an IC. One reason for this difficulty is that salphasic clocking generally requires a low loss transmission medium to maintain a dominant standing wave. On-die interconnects, however, have traditionally been relatively lossy structures. In an ideal lossless system, standing waves include abrupt 180 degree phase changes at specific locations on the corresponding transmission medium. When loss is introduced, however, the abruptness of the phase changes are reduced, creating regions of unacceptable phase differences on the medium. These phase differences can introduce a significant amount of clock skew to the system. In addition, the inherent position dependent amplitudes associated with salphasic clocking techniques can also introduce skew, even in a relatively lossless system.


REFERENCES:
patent: 5387885 (1995-02-01), Chi
patent: 5410491 (1995-04-01), Minami
patent: 5497109 (1996-03-01), Honda et al.
patent: 5519351 (1996-05-01), Matsumoto
patent: 5521541 (1996-05-01), Okamura
patent: 5570045 (1996-10-01), Erdal et al.
patent: 5668484 (1997-09-01), Nomura
patent: 5691662 (1997-11-01), Soboleski et al.
patent: 5717229 (1998-02-01), Zhu
patent: 6043704 (2000-03-01), Yoshitake
patent: 6150865 (2000-11-01), Fluxman et al.
patent: 6157688 (2000-12-01), Tamura et al.
patent: 6211714 (2001-04-01), Jeong
patent: 6255884 (2001-07-01), Lewyn
patent: 6311313 (2001-10-01), Camporese et al.
patent: 6323714 (2001-11-01), Naffziger et al.
patent: 6429714 (2002-08-01), Schultz

Affiliated with

Also associated with

Rating

Hierarchical clock grid for on-die salphasic clocking does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Hierarchical clock grid for on-die salphasic clocking, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Hierarchical clock grid for on-die salphasic clocking will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3161350