Hierarchical clock gating circuit and method

Details Hierarchical clock gating circuit and method Hierarchical clock gating circuit and method

2005-01-18

2005-01-18

Wells, Kenneth B. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Clock or pulse waveform generating

C327S295000

Reexamination Certificate

active

06844767

ABSTRACT:
A power saving hierarchical clock gating circuit includes a first level clock gate, a plurality of second level clock gates connected to the first level clock gate, and a plurality of third level clock gates for selectively providing a clock signal to a functional block. Each third level clock gate is connected between a second level clock gate and a register, or other low level device, of the functional block for selectively providing the clock signal to the register. Accordingly, the clock signal is conveyed from the first level clock gate through a second level and a third level clock gate to a register when the corresponding first, second, and third level clock gates are activated by associated decision logic.

REFERENCES:
patent: 5815725 (1998-09-01), Feierbach
patent: 6583648 (2003-06-01), Cai
patent: 6611920 (2003-08-01), Fletcher et al.

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