Hierarchical cache memory system and method

Details Hierarchical cache memory system and method Hierarchical cache memory system and method

1985-06-27

1988-07-05

Harkcom, Gary V.

Boots, shoes, and leggings

G06F 1208, G06F 1212

Patent

active

047559306

ABSTRACT:
A caching system for a shared bus multiprocessor which includes several processors each having its own private cache memory. Each private cache is connected to a first bus to which a second, higher level cache memory is also connected. The second, higher level cache in turn is connected either to another bus and higher level cache memory or to main system memory through a global bus. Each higher level cache includes enough memory space so as to enable the higher level cache to have a copy of every memory location in the caches on the level immediately below it. In turn, main memory includes enough space for a copy of each memory location of the highest level of cache memories. The caching can be used with either write-through or write-deferred cache coherency management schemes.

REFERENCES:
patent: 4136386 (1979-01-01), Annunziata et al.
patent: 4141067 (1979-02-01), McLagan
patent: 4144566 (1979-03-01), Timsit
patent: 4157586 (1979-06-01), Gannon et al.
patent: 4161024 (1979-07-01), Joyce et al.
patent: 4228503 (1980-10-01), Waite et al.
patent: 4322795 (1982-03-01), Lange et al.
patent: 4442487 (1984-04-01), Fletcher et al.
patent: 4445174 (1984-04-01), Fletcher
patent: 4464712 (1984-08-01), Fletcher
patent: 4464717 (1984-08-01), Keeley et al.
patent: 4489381 (1984-12-01), Lavallee et al.
patent: 4530055 (1985-07-01), Hamstra et al.
patent: 4577293 (1986-03-01), Matick et al.
Bell, J.; Cassassent, D.; and Bell, C. G.; "An Investigation of Alternate Cache Organization" IEEE Transactions on Computing, Apr., 1974.
Chow, C. K.; "Determination of Cache's Capacity and its Maturing Storage Hierarchy", IEEE Transactions on Computers (C-25), Feb., 1976.
Dubois, Michael, and Briggs, F. A.; "Effects of Cache Coherency in Multiprocessors"; IEEE Transactions on Computers C-31(11), Nov., 1982.
Easton, M. C.; "Computation of Cold-Start Miss Rations" IEEE Transactions on Computers C-27 (5), May, 1978.
Frank, S. J.; "A Tightly Coupled Multiprocessor System Speeds Memory-Access Timer"; Electronics: 164-169, Jan., 1984.
Goodman, J. R.; "Using Cache Memory to Reduce Processor-Memory Traffic", in 10th Annual Symposium on Computer Architecture, 1983.
Papamarcos, M. S., and Patel, J. M.; "A Low Overhead Coherence Solution for Multiprocessors with Private Cache Memories" in 11th Annual Symposium Computer Architecture, 1984.
Patel, J. H.; "Analysis of Multiprocessors with Private Cache Memories" IEEE Transactions on Computers, C-31(4): 296-304, Apr., 1982.
Pohm, A. V., and Agrawal, O. P.; High-Speed Memory Systems Reston Publishing Company, Inc., 1983.
Rao, G. S.; "Performance Analysis of Cache Memories"; Journal of the ACM 25, 1978.
Rudolph, L. and Segall, Z.; "Dynamic Decentralized Cache Scheme for MINK Parallel Processors"; in 11th Annual Symposium on Computer Architecture, 1984.
Smith, A. J.; "A Comparative Study of Set Associative Memory Mapping Algorithm and Their Use for Cache and Main Memory", IEEE Transactions on Software Engineering SE-4(5), Mar., 1978.
Smith, A. J.; "Cache Memories", Computing Surveys, 14(3), Sep. 1982.
Smith, J. E., Goodman, J. R.; "A Study of Instruction Cache Organizations and Replacement Policies", In 10th Annual Symposium on Computer Architecture, 1983.
Strecker, W. D.; "Transient Behavior of Cache Memories", ACM Transactions on Computer Systems (4), Nov., 1983.
Tang, C. K.; "Cache System Design in the Tightly Coupled Multiprocessor System", in AFIPS Proceedings. 1976.
Wulf, W. A., Levin, R., and Harbison, S. P.; Hydra/C.mmp An Experimental Computer System; McGraw-Hill Book Company, 1981.
Censier, L. M., and Feautrier, P.; "A New Solution to Coherence Problems in Multicache Systems", IEEE Transactions on Computers, vol. c-27, No. 12, Dec., 1978.
Yen, W. C., and Fu, K. S.; "Analysis of Multiprocessor Cache Organizations with Main Memory Update Policies", IEEE, 1981, pp. 89-105.

Affiliated with

Also associated with

Rating

Hierarchical cache memory system and method does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Hierarchical cache memory system and method, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Hierarchical cache memory system and method will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2336536