Hierarchical cache memory apparatus

Details Hierarchical cache memory apparatus Hierarchical cache memory apparatus

1990-03-28

1993-08-31

Bowler, Alyssa H.

Boots, shoes, and leggings

364DIG1, 364964343, 36424341, G06F 1200, G06F 1208, G06F 1300

Patent

active

052416410

ABSTRACT:
A hierarchical cache memory apparatus assembled in a multiprocessor computer system including a plurality of processors and a memory device, includes a plurality of first cache memory devices arranged in correspondence with the plurality of processors and each including a controller including a first status identification section for identifying status of each of a plurality of pieces of address information, a plurality of first connection devices for connecting the plurality of first cache memory devices in units of a predetermined number of devices to constitute a plurality of mini-cluster devices a plurality of second cache memory devices respectively connected to the first connection devices in correspondence with the plurality of mini-cluster devices, having all the addresses of address information of the plurality of first cache memory devices in the mini-cluster devices, and each comprising a controller including a second status identification section for identifying status of each of the plurality of address information, and a memory device connected to the second connection devices and having all the addresses of the plurality of address information of the plurality of second cache memory devices.

REFERENCES:
patent: 4755930 (1988-07-01), Wilson, Jr. et al.
patent: 4928225 (1990-05-01), McCarthy et al.
"Using Cache Memory to Reduce Processor-Memory Traffic", by James Goodman, Sigarch Newsletter vol. 11, No. 3, Jun. 13-17, 1983.
"Cache Memories", by Jay Smith, Computing Surveys vol. 14, No. 3, Sep. 1982.
Cache Coherence Protocols: Evaluation Using a Multiprocesser Simulation Method, Archibald et al. ACM Transactions vol. 4, No. 4, Nov. 1986, pp 273-298.
Gaetano Borriello et al., Report No. UCB/CSD 84/199 Sep. 1984, pp. 1-89, "Design and Implementation of an Integrated Snooping Data Cache".
Wilson, Jr., 14th I.S.C.A., vol. 15, No. 2, Jun. 1987, pp. 244-252 "Hierarchical Cache/Bus Architecture for Shared Memory Multiprocessors".

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