Hierarchical buffer memories for selectively controlling data co

Details Hierarchical buffer memories for selectively controlling data co Hierarchical buffer memories for selectively controlling data co

1994-10-05

1997-06-03

Kim, Matthew M.

395472, 395449, G06F 1208

Patent

active

056363656

ABSTRACT:
A buffer-memory coherence control mechanism for a data processing system includes a coherence control identification device. For each entry of a second buffer memory to which a plurality of first buffer memories is connected, a control bit for coherence control is stored in a control bit table. The control bit table is provided with 1 bit corresponding to each first buffer memory and indicates which first buffer memory shares a block corresponding to the second buffer memory. When coherence control between the first buffer memories is needed, a coherence control request is issued according to the content of the control bit table only to a specified first buffer memory. In addition, even if a block was cast out of the first buffer memory, the control bit table would not be updated.

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