Hierarchical bit line arrangement in a semiconductor memory

Details Hierarchical bit line arrangement in a semiconductor memory Hierarchical bit line arrangement in a semiconductor memory

1996-06-17

1997-10-28

Clawson, Jr., Joseph E.

Static information storage and retrieval

Interconnection arrangements

365190, 365203, 365208, 365210, 36523003, 36523006, G11C 506

Patent

active

056823436

ABSTRACT:
Main bit lines MBL and ZMBL are disposed at opposite sides of a sense amplifier SA. Main bit lines MBL and ZMBL each are provided for paired sub-bit lines SBL1 and SBL2 (or SBL3 and SBL4). Sub-bit line pair SBL1 and SBL2 is connected to main bit line MBL via a block select switch T1. Sub-bit line pair SBL3 and SBL4 is connected to main bit line ZMBL via a block select switch T2. Since one main bit line is provided for two sub-bit lines, a pitch of the main bit lines is twice as large as a pitch of the sub-bit lines, so that conditions on the pitch of main bit lines are remarkably eased, which facilitates layout of elements.

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patent: 5140555 (1992-08-01), Nishiguchi et al.
patent: 5363331 (1994-11-01), Matsui et al.
patent: 5386394 (1995-01-01), Kawahara et al.
patent: 5424977 (1995-06-01), Rountree

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