Hierarchical, adaptable-configuration dynamic random access memo

Details Hierarchical, adaptable-configuration dynamic random access memo Hierarchical, adaptable-configuration dynamic random access memo

1998-06-30

1999-11-02

Nelms, David

Static information storage and retrieval

Addressing

Plural blocks or banks

365200, 36523002, 36523006, G11C 800

Patent

active

059783044

ABSTRACT:
A DRAM memory array is organized hierarchically into groups of DRAM segments, bit blocks within segments, and memory cells within bit blocks, arranged in rows and columns. A control and logic circuit extends along the rows and columns and segment buses extend from the control and logic circuit to the DRAM segments. Partial decoding of the address and control signals occurs in the control and logic circuit and the partially decoded control and address signals are supplied on the segment buses. Adaptable memory operations are controlled in the control and logic circuit, such as redundant element substitution, data block addressing, multiplexing of the data bit width signals available at the DRAM segments to the width required by a system bus. This flexibility allows various physical organizations of the DRAM array.

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