Hierarchial power network simulation and analysis tool for relia

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G06F 1100

Patent

active

058780530

ABSTRACT:
The present invention pertains to a method for analyzing a semiconductor chip design for determining potential voltage drop and electromigration problems. Initially, the semiconductor chip design is divided into a plurality of blocks. A block level verification is then performed based on the assumption that full voltage is being supplied to each of the blocks. Next, the blocks are modeled by an equivalent RC network. This RC network is then reduced into a simpler representation. The voltage drops are determined based on the reduced, equivalent model. The blocks are then reanalyzed with the supply voltage input to the blocks reduced according to the calculated voltage drops. Thereby, a more realistic simulation can be achieved.

REFERENCES:
patent: 5585765 (1996-12-01), O'Shaughnessy
patent: 5592118 (1997-01-01), Wilmot et al.

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