Hiding irrelevant facts in verification conditions

Details Hiding irrelevant facts in verification conditions Hiding irrelevant facts in verification conditions

2011-04-12

2011-04-12

Yigdall, Michael J (Department: 2192)

Data processing: software development, installation, and managem

Software program development tool

Testing or debugging

C717S124000, C717S131000, C717S132000, C717S136000, C717S137000, C717S143000, C717S157000, C717S159000

Reexamination Certificate

active

07926037

ABSTRACT:
A program verification process begins by converting a language of the program from a first language into an intermediate language representation. The loops of the program are eliminated. The program is converted from the intermediate language representation into a passive form. Dominators for the passive form of the program are determined. A verification condition is generated from the passive form of the program. The verification condition is structured according to the computed dominators such that when a theorem prover identifies a potential error, portions of the passive form of the program irrelevant to the potential error are ignored.

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The Spec# Programming System: An Overview Author: Mike Barnett, K. Rustan M.Leino, Wolfarm Schulte Manuscript KRML136, Oct. 12, 2004. To Appear in CLASSIS 2004 Preceeding.
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