Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Of specified material other than unalloyed aluminum
Reexamination Certificate
2001-05-17
2003-07-08
Ho, Hoai (Department: 2818)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Of specified material other than unalloyed aluminum
C257S760000
Reexamination Certificate
active
06590289
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to the art of microelectronic integrated circuits. In particular, the present invention relates to the art of using multiple layers of metals to route the cells in integrated circuits.
2. Description of the Prior Art
The fabrication of semiconductor devices has progressed significantly over the last four decades. Some semiconductor chips incorporate over a million transistors. However, the demand for more functionality will require an increase in the number of transistors that need to be integrated on a chip. This will require shrinking the area required to fabricate interconnected transistors or will require larger die sizes, or both. As the feature size decreases and the area required to fabricate transistors decreases, the resulting increased density of devices will require an increasing number of interconnections within a chip, or interconnections between chips in a multi-chip design.
Transistors or gates typically make up a circuit cell. Each cell of an integrated circuit includes a plurality of points, sometimes referred to as pins or terminals, each of which must be connected to pins of other cells by an electrical interconnect wire network or net. Cells may comprise individual logic gates or, more preferably, may each comprise a plurality of gates or transistors that are interconnected to form functional blocks. It is desirable to attempt to optimize a design so that the total wire length and interconnect congestion are minimized.
As the number of transistors on a single chip becomes very large, gains made in reducing the feature size brought on by advances in fabrication technology may be offset by the increased area required for interconnection. As the number of interconnections increase, the amount of real estate on the semiconductor die occupied by interconnections could become relatively large unless steps are taken to improve conventional layout techniques.
In early days of large scale integration, only a single layer of metal was available for routing, and polysilicon (polycrystalline silicon) and a single such metal layer were used to complete the interconnections. The first metal layer may be referred to as the “metal 1” layer or “M1” layer. As semiconductor fabrication processes improved, a second metal layer was added. The second metal layer may be referred to as the “metal 2” layer or “M2” layer.
The performance of a chip depends on the maximum wire length of the interconnection metal used. For better performance, it is desirable to minimize the maximum wire length. As the feature size is made smaller, the delay per unit length of interconnection increases.
The performance of a chip is bound by the time required for computation by the logic devices and the time required for the data communication. In the past, the time required for data communication was typically insignificant compared to the time required for computation, and could be neglected. In the past three decades, there has been a significant improvement in the average speed of computation time per gate. Now, the interconnection delays are on the order of gate delays and as a result, have become significant and can no longer be ignored. Interconnect delays are an increasing percentage of path delay.
When two points are interconnected by metal, a connection is formed which may be referred to as a wire or a conductor. When two wires in the same metal layer run parallel to each other, parasitic capacitances may be significant and “crosstalk” may occur between signals on those wires. The metal 1 layer is typically separated from the metal 2 layer by a dielectric. When only two metal layers were used, a rectangular or rectilinear approach to routing provided metal 1 wires at 90 degrees relative to metal 2 wires, and this gave satisfactory results in many instances. However, a rectangular approach to routing when three metal layers are available has provided metal 3 wires parallel to metal 1 wires, and these metal layers are separated by layers of dielectric. This has resulted in unsatisfactory capacitance and “crosstalk” in many instances. With four metal layers, metal layers M1 and M3 may have parallel wires, and metal layers M2 and M4 may have parallel wires or conductors. Significant performance degradation may result.
Microelectronic integrated circuits consist of a large number of electronic components that are fabricated by layering several different materials on a silicon base or wafer. The design of an integrated circuit transforms a circuit description into a geometric description which is known as a layout. A layout consists of a set of planar geometric shapes in several layers.
Typically, the layout is then checked to ensure that it meets all of the design requirements. The result is a set of design files in a particular unambiguous representation known as an intermediate form that describes the layout. The design files are then converted into pattern generator files that are used to produce patterns by an optical or electron beam pattern generator that are called masks.
During fabrication, these masks are used to pattern a silicon wafer using a sequence of photolithographic steps. This component formation requires very exacting details about geometric patters and separation between them. These details are expressed by a complex set of design rules. The process of converting the specifications of an electrical circuit into a layout is called the physical design. It is an extremely tedious and an error-prone process because of the tight tolerance requirements, the complexity of the design rules, and the minuteness of the individual components.
Currently, the geometric feature size of a component is on the order of 0.5 microns. However, it is expected that the feature size can be reduced to 0.1 micron within several years. This small feature size allows fabrication of as many as 4.5 million transistors or 1 million gates of logic on a 25 millimeter by 25 millimeter chip. This trend is expected to continue, with even small feature geometries and more circuit elements on an integrated circuit, and of course, larger die (or chip) sizes will allow far greater numbers of circuit, elements.
As stated above, each microelectronic circuit cell includes a plurality of pins or terminals, each of which must be connected to the pins of other cells by a respective electrical interconnect wire network or net. A goal of the optimization process is to determine a cell placement such that all of the required interconnects can be made, and the total wirelength and interconnect congestion are minimized. A goal of routing is to minimize the total wirelength of the interconnects, and also to minimize routing congestion. Achievement of this goal is restricted using conventional rectilinear routing because diagonal connections are not possible. Rarely are points to be connected located in positions relative to each other such that a single straight wire segment can be used to interconnect the points. Typically, a series of wire segments extending in orthogonal directions have been used to interconnect points. A diagonal path between two terminals in shorter than two rectilinear orthogonal paths that would be required to accomplish the same connection. Another drawback of conventional rectilinear interconnect routing is its sensitivity to parasitic capacitance. Since many conductors run in the same direction in parallel with each other, adjacent conductors form parasitic capacitances that can create signal crosstalk and other undesirable effects.
As illustrated in
FIG. 1
, a conventional microelectronic integrated circuit
93
comprises a substrate
95
on which a large number of semiconductor devices are formed. These devices include large functional macroblocks such as indicated at
94
which may be central processing units, input-output devices or the like. Many designers have a cell library consisting of standardized cells that perform desired logical operations, and which may be combined with other cells to form an int
Ho Hoai
LSI Logic Corporation
Mitchell Silberberg & Knupp LLP
Tran Long
LandOfFree
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