Heuristic digital processor using non-linear transformation

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395 24, 395 27, 36493101, 3642749, G06F 738

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054757932

ABSTRACT:
A heuristic processor incorporates a digital arithmetic unit arranged to compute the squared norm of each member of a training data set with respect to each member of a set of centers, and to transform the squared norms in accordance with a non-linear function to produce training .phi. vectors. A systolic array arranged for QR decomposition and least means squares processing forms combinations of the elements of each .phi. vector to provide a fit to corresponding training answers. The form of combination is then employed with like-transformed test data to provide estimates of unknown results. The processor is applicable to provide estimated results for problems which are non-linear and for which explicit mathematical formalisms are unknown.

REFERENCES:
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patent: 4893255 (1990-01-01), Tomlinson, Jr.
patent: 5018065 (1991-05-01), McWhirter et al.
Military Microwaves '88, Jul. 1988, "The Experimental Verification of the Performance of a Systolic Array Adaptive Processor," Hargrave et al., pp. 521-526.
Jet Propulsion Laboratory, Mopenn et al., "A Neural Network for Euclidean Distance Minimization," pp. II-349-II-356.

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