Heterojunction field effect transistor

Details Heterojunction field effect transistor Heterojunction field effect transistor

1997-10-27

2002-07-30

Mintel, William (Department: 2811)

Active solid-state devices (e.g., transistors, solid-state diode

Heterojunction device

Field effect transistor

C257S194000, C257S195000, C438S172000

Reexamination Certificate

active

06426523

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to a field effect transistor (FET) and a fabrication process thereof. More particularly, the invention relates to a hetero junction FET and a fabrication process thereof.
2. Description of the Related Art
Conventionally, GaAs FETs have been widely employed as elements for high frequency. Particularly, in a high power element, in order to reliably achieve reduction of source resistance and higher gate breakdown voltage(gate tolerance voltage), a multi-stage recessed structure has been employed.
FIGS. 1A
to
1
D are sections showing a recess formation process of a conventional GaAs FET, illustrating the process steps in sequential order. As shown in
FIG. 1A
, a channel layer
2
consisting of undoped InGaAs or undoped GaAs, is formed on a GaAs layer
1
. On the channel layer
2
, an Si doped AlGaAs layer
3
is formed. On the AlGaAs layer
3
, an Si doped GaAs layer
4
is formed. Also, a wide recess
6
is formed by patterning the GaAs layer
4
employing a mask
5
.
Next, as shown in
FIG. 1B
, a mask
7
is formed covering the upper surface and side surface of the GaAs layer
4
after patterning. Using the mask
7
, an upper half of the AlGaAs layer
3
is patterned to form a recess
8
for a gate.
Subsequently, as shown in
FIG. 1C
, a gate electrode
9
is buried in the recess
8
. Furthermore, as shown in
FIG. 1D
, after removing the mask
7
, a source electrode
10
and a drain electrode
11
are selectively formed on the GaAs layer
4
.
As set forth above, in a fabrication process of conventional multi-stage recessed structure, the recesses are formed by patterning the masks per each stage and wet etching process with an etching liquid containing sulfuric acid as primary component.
However, in the fabrication process of a FET of the multi-stage recessed structure, exposure steps in number corresponding to number of recesses are required. On the other hand, since wet etching is performed every time of formation of the recess, fluctuation of etching can cause degradation of uniformity and reproduction ability of FET characteristics (particularly threshold voltage).
Particularly, in
FIG. 1B
, the shape of the recess
8
formed by etching immediately before providing the gate, significantly influences threshold value.
On the other hand, there has been proposed a recess forming technology by selective dry etching of the GaAs layer using the InGaAs layer or AlGaAs layer as an etching stopper (Japanese Unexamined Patent Publication No. Heisei 4-280640). However, a conventional recess forming process by the selective dry etching is primarily directed to realization of the threshold value with high uniformity and no consideration is given for improvement of the FET characteristics per se.
On the other hand, in “High Efficiency Power Module Using HEMT for PDC”, Preliminary Report of 1996 Institute of Electronics, Communication and Information, Electron-Science Meeting, C-422, there has been disclosed a multistage recessed InGaAS/AlGaAs HEMT, in which an etching stopper layer consisted of n
−
AlGaAs is provided between an n
+
GaAs layer and an n
−
GaAs layer to perform selective etching to form the recessed structure with good controllability and reproduction ability. On the other hand, in
FIG. 1
of the above-identified publication, there is disclosed a structure, in which a gate metal and a neighborhood semiconductor layer are not contacted.
In the above-identified known publication, there is no disclosure of a fabrication process of the HEMT. Thus, assuming from the structure, since the mask for forming the gate metal is formed after formation of the two stage recessed structure through at least two lithographic steps, at least three lithographic steps are necessary.
SUMMARY OF THE INVENTION
It is an object of the present invention to improve FET characteristics by improving an electrode structure of an FET.
Another object of the present invention is to provide a fabrication process of an FET with lesser fluctuation of characteristics of the FET, such as threshold value or so forth, with lower rising voltage, achieving a hetero junction FET structure having high breakdown voltage (tolerance voltage) characteristics with high uniformity and reproduction ability, and with high yield.
A further object of the present invention is to provide a fabrication process of an FET, in which a gate portion of a hetero junction FET of a multi-stage recessed structure having good characteristics, or an ohmic electrode having a lower contact resistance of the FET can be formed simply with high uniformity and reproduction capacity.
A first aspect of the field effect transistor according to the present invention comprises: a hetero junction semiconductor crystal having at least a channel layer of InGaAs or GaAs, a first AlGaAs layer. a first GaAs layer, a second AlGaAs layer and an n-type second GaAs layer; and an ohmic electrode contacting with said second GaAs layer and said channel layer or with said second GaAs layer and said first AlGaAs layer doped with a donor.
Also, said field effect transistor may-include a gate electrode having a two stage recess structure, in which said first and second GaAs layers are removed in stepwise fashion in the vicinity of said gate electrode forming portion, said gate electrode having a gap between said first GaAs layer and said gate electrode on said first AlGaAs layer, whereby said gate electrode does not contact said first GaAs layer.
A second aspect of the field effect transistor according to the present invention comprises: a hetero junction semiconductor crystal at least including a channel layer of InGaAs or GaAs, a first AlGaAs layer, a first GaAs layer, a second AlGaAs layer and an n-type second GaAs layer, said hetero junction semiconductor crystal having a two stage recess structure removed from said first and second GaAs layers in stepwise fashion in the vicinity of a gate electrode forming portion; and a gate electrode having a gap on said first AlGaAs layer and between said first GaAs layer and said gate electrode, so as to not contact said gate electrode with said first GaAs layer, a gap between a drain region side of said gate electrode and said first GaAs layer being greater than said gap between the source region side of said gate electrode and said first GaAs layer.
A third aspect of the field effect transistor according to the present invention comprises: a hetero junction semiconductor crystal at least including a channel layer of InGaAs or GaAs, a first AlGaAs layer, a first GaAs layer, a second AlGaAs layer and an high concentration n-type second GaAs layer, said hetero junction semiconductor crystal having a two stage recess structure removed from said first and second GaAs layers in stepwise fashion in the vicinity of a gate electrode forming portion; and a gate electrode having a gap on said first AlGaAs layer and between said first GaAs layer and said gate electrode, so as to not contact said gate electrode with said first GaAs layer, a gap between the source region side of said gate electrode and said first GaAs layer being greater than a gap between the drain region side of said gate electrode and said first GaAs layer.
A fourth aspect of the field effect transistor according to the present invention comprises: a hetero junction semiconductor crystal at least including a channel layer of InGaAs or GaAs, an AlGaAs layer, a layer of InAlAs or InAlGaAs and an n-type GaAs layer, said hetero junction semiconductor crystal having a two stage recess structure removed from said n-type GaAs layer and a layer of InAlAs or InAlGsAs in the vicinity of a gate electrode; and a gate electrode provided on said AlGaAs layer, defining a gap between said gate electrode and said layer of InAlAs or InAlGaAs so as to not contact said gate electrode with said layer of InAlAs or InAlGaAs.
The width of said gap between the drain region side of said gate electrode and the layer of InAlAs or InAlGaAs may be different from the width of said ga

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