Heterojunction field effect transistor

Active solid-state devices (e.g. – transistors – solid-state diode – Heterojunction device – Field effect transistor

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Details

257190, 257191, 257194, H01L 31072, H01L 31109, H01L 310328, H01L 310336

Patent

active

052850870

ABSTRACT:
A heterojunction field effect transistor includes a semi-insulating crystalline layer, a pseudomorphic channel layer disposed on the semi-insulating crystalline layer, and an electron supply layer disposed on said pseudomorphic layer. The channel layer has a lattice constant equal to or close to that of the semi-insulating crystalline layer adjacent to semi-insulating crystalline layer and different from the semi-insulating crystalline layer adjacent to the electron supply layer.

REFERENCES:
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patent: 4764796 (1988-08-01), Sasaki et al.
patent: 4823171 (1989-04-01), Matsui
patent: 4827320 (1989-05-01), Morkoc et al.
patent: 4894691 (1990-01-01), Matsui
patent: 4967242 (1990-10-01), Sonoda et al.
patent: 5049951 (1991-09-01), Goronkin et al.
patent: 5099295 (1992-03-01), Ogawa
patent: 5124762 (1992-06-01), Childs et al.
IEEE Transactions on Electron Devices, vol. 37, No. 6, Jun. 1990, "An AlGaAs/In.sub.x Ga.sub.1-x As/AlGaAs (0.ltoreq.x.ltoreq.0.5) Pseudomorphic HEMT on GaAs Substrate Using an In.sub.x/2 Ga.sub.1-x/2 As Buffer Layer", by Maezawa et al., pp. 1416-1421.
IEEE Transactions on Electron Devices, vol. 36, No. 11, Nov. 1989, "Quantum-Well p-Channel AlGaAs/InGaAs/GaAs Heterostructure Insulated-Gate Field-Effect Transistors", by Ruden et al., pp. 2371-2379.

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