Heterojunction field effect transistor

Active solid-state devices (e.g. – transistors – solid-state diode – Heterojunction device – Field effect transistor

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Details

257 24, 257196, 257 27, H01L 2906, H01L 310328, H01L 31072, H01L 31109

Patent

active

055833535

ABSTRACT:
A heterojunction FET includes an electron supply layer formed on a non-doped semiconductor layer serving as a channel forming layer and a current path forming layer formed on the electron supply layer. The electron supply layer has an energy band gap greater than the non-doped semiconductor layer and its portion under a gate electrode is always depleted at any gate bias voltage in a bias voltage range for operating of the field effect transistor. The current path forming layer has a larger electron mobility than the electron supply layer. The gate electrode is formed on the current supply layer. Under a high gate bias voltage condition, parallel conduction does not occur in the electron supply layer but does occur in the current path forming layer. Since the current path forming layer has a larger carrier mobility than the electron supply layer, the mutual conductance value is kept high.

REFERENCES:
patent: 4663643 (1987-05-01), Mimura
patent: 4882608 (1989-11-01), Smith, III
patent: 5283448 (1994-02-01), Bayraktaroglu
patent: 5381027 (1995-01-01), Usagawa et al.

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