Heterojunction FET having barrier layer consisting of two layers

Details Heterojunction FET having barrier layer consisting of two layers Heterojunction FET having barrier layer consisting of two layers

1994-12-20

1996-08-27

Crane, Sara W.

Active solid-state devices (e.g., transistors, solid-state diode

Thin active physical layer which is

Heterojunction

257190, 257194, H01L 2906

Patent

active

055503888

ABSTRACT:
A heterojunction FET disclosed herein includes a semi-insulating GaAs substrate, a buffer layer composed of an undoped In.sub.y/2 Al.sub.1-y/2 As layer (0<y<1), and having a film thickness less than or equal to a critical film thickness, a first barrier layer composed of an undoped AlAs layer and an undoped In.sub.y Al.sub.1-y As layer (0<y<1), a channel layer composed of an undoped In.sub.y Ga.sub.1-y As layer (0<y<1), a second barrier layer composed of an N-type In.sub.y Al.sub.1-y As layer (0<y<1), each layer disposed in the order mentioned, on the semi-insulating GaAs substrate, a gate electrode which is selectively disposed on the second barrier layer to form a Schottky junction, and electrodes for a drain and a source, each of which is disposed on the second barrier layer via a contact layer, with said gate electrode therebetween.

REFERENCES:
patent: 5343057 (1994-08-01), Gerard et al.
patent: 5367182 (1994-11-01), Matsugatani et al.
patent: 5373168 (1994-12-01), Ando et al.
Maezawa et al., "An AlGaAs/In.sub.x Ga.sub.1-x As/AlGaAs (0<x<0.5) Pseudomorphic HEMT on GaAs Substrate Using an In.sub.x/2 Ga.sub.1-x/2 As Buffer Layer," IEEE Transactions on Electron Devices, vol. 37, No. 6, Jun. 1990, pp. 1416-1421.

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