Heterojunction bipolar transistors with extremely low offset...

Details Heterojunction bipolar transistors with extremely low offset... Heterojunction bipolar transistors with extremely low offset...

2003-08-08

2004-10-05

Tran, Minhloan (Department: 2826)

Active solid-state devices (e.g., transistors, solid-state diode

Heterojunction device

Bipolar transistor

C257S198000, C257S565000, C257S578000, C257S590000, C257S591000, C438S312000, C438S343000

Reexamination Certificate

active

06800880

ABSTRACT:

FIELD OF THE INVENTION
This invention is related to Heterojunction Bipolar Transistor (HBT), especially the new HBT featuring extremely low offset voltage and high current gain.
BACKGROUND OF THE INVENTION
In the past years, Heterojunction Bipolar Transistors (HBT's) made up of compound semiconductor has been in widespread use for microwave, high-speed and power circuit fields. In industries of emerging personal communication, satellite communication, and wireless data transmission, the device based on InP substrate is suitable for optical integrated circuit application, while HBT whose base is made up of GaInAs has been popularly applied to reduce the transient time and to increase operating frequency range. In addition, because the surface combination rate of GaInAs base is very low, the combined current on the surface of the junction is reduced, and the current gain is raised. Also, the reliability is increased because of the independent relationship between the transistor's characteristic and the area size of the device. However, as far as conventional AlInAs/GaInAs HBT's are concerned, the conduction band discontinuity (&Dgr;E
C
) at the AlInAs/GalnAs junction is quite large (about 0.55 eV), so the potential spike at the base-emitter junction will make the offset voltage (&Dgr;V
CE
) at the collector-emitter junction so high as to dissipate the usable power for circuit applications. This disadvantage makes it unsuitable for integrated circuit's operation. As for InP/GaInAs HBT's, the valence band discontinuity (&Dgr;E
V
) at the InP/GaInAs junction is quite large (about 0.35 eV). So, the confinement effect for holes, the emitter injection efficiency, and the current gain are pretty high. However, although the conduction band discontinuity (&Dgr;E
C
) at the InPlGalnAs junction is smaller than that of the AlInAs/GaInAs junction, it is, still a little large (about 0.25 eV) such that the offset voltage (&Dgr;V
CE
) at the collector-emitter junction can't be neglected. In the past, a lot of countries devoted themselves to the cutting-edge research and development of the HBT's, and a variety of practical HBT devices with characteristics of high current gain and extremely low offset voltage are presented, such as all kinds of Heterostructure Emitter Bipolar Transistor (HEBT), GaInP/GaAs double HBT's (DHBT's), Resonant-Tunneling Heterojunction-Emitter Bipolar Transistors (RT-HEBT's), Spacer HBT's, and &dgr;-doped Heterojunction Bipolar Transistors (&dgr;-HBT's). The aforementioned devices already had remarkable experimental performances. In the last few years, inventors who have worked on AlInAs/GaInAs HEBT found that inserting a 500 Å n-GaInAs emitter layer into the n-AlInAs/p
+
-GaInAs base-emitter junction makes its offset voltage down to only 40 mV. But the diffusion distance of the holes of the GaInAs is so narrow that the electron-hole at the neutralized emitter region combines with each other easily. Thus the current gain is decreased with the increment of the base current. European Patent Publication No. 0778622 (1997) discloses a new Heterojunction Bipolar Transistor (HBT). In this invention, a &dgr;-doped/spacer layer is inserted into the base-emitter heterojunction to eliminate the potential spike and to raise the current gain. However, the doping concentration of the &dgr;-doped layer has to reach extraordinarily high so that the potential spike can be eliminated completely and effectively. Besides, the &dgr;-doping may diffuse out to the large energy-gap emitter layer, so it is unfavorable for the completeness and the quality of the base-emitter heterojunction.
SUMMARY OF THE INVENTION
This invention discloses one new Heterojunction Bipolar Transistors (HBT's) with characteristics of high current gain and extremely low offset voltage. In the present invention, the spacer/&dgr;-doped/spacer layer is inserted into the base-emitter heterojunction. It can eliminate the potential spike and enhance the confinement effect for holes. More importantly, the potential spike of the HBT's in the present invention can be eliminated completely and effectively without the highly doped concentration of the &dgr;-doped. Besides, when the base-emitter bias is very high, the potential spike still doesn't appear and the offset voltage is still low. These advantages can help to improve the device characteristics on circuit applications, especially for the HBT's with large conduction band discontinuity (&Dgr;E
C
). In addition, the device of the present invention is easy to be implemented and stable to operate at room temperature.
A structure of heterojunction bipolar transistor constructed according to one aspect of the present invention comprises a semi-insulated InP semiconductor substrate, a n
+
subcollector layer on said semi-insulated InP semiconductor substrate, a n
−
collector layer on said n
+
subcollector layer, a p
+
base layer on said n
−
collector layer, a first non-doped spacer layer on said p
+
base layer, a n
+
&dgr;-doped layer on said first non-doped spacer layer, a second non-doped spacer layer on said n
+
&dgr;-doped layer, a n-type emitter layer on said second non-doped spacer layer, and a n
+
ohmic contact layer on said n-type emitter layer.
Preferably, said n
+
subcollector layer is Ga
0.47
In
0.53
As, and has a thickness of 0.2 to 1 &mgr;m, and a concentration of n=1×10
18
to 3×10
19
cm
−3
.
Preferably, said n
−
collector layer is Ga
0.47
In
0.53
As, and has a thickness of 0.2 to 1 &mgr;m, and a concentration of n
−
=1×10
16
to 1×10
17
cm
−3
.
Preferably, said p
+
base layer is Ga
0.47
In
0.53
As, and has a thickness of 0.05 to 0.2 &mgr;m, and a concentration of p=1×10
18
to 4×10
19
cm
−3
.
Preferably, said first non-doped spacer is Ga
0.47
In
0.53
As, and has a thickness of 10 to 200 Å.
Preferably, said n
+
&dgr;-doped layer has a concentration of &dgr;(n
+
)=1×10
12
to 1 ×10
13
cm
−3
.
Preferably, said second non-doped spacer is Ga
0.47
In
0.53
As, and has a thickness of 10 to 200 Å.
Preferably, said n-type emitter layer is InP or Al
0.48
In
0.52
As, and has a thickness of 0.05 to 0.2 &mgr;m, and a concentration of n=1×10
17
to 1×10
18
cm
−3
.
Preferably, said n
+
ohmic contact layer is Ga
0.47
In
0.53
As, and has a thickness of 0.1 to 0.5 &mgr;m, and a concentration of n=1×10
18
to 3×10
19
cm
−3
.
A structure of heterojunction bipolar transistor constructed according to another aspect of the present invention comprises a semi-insulated GaAs semiconductor substrate, a n
+
subcollector layer on said semi-insulated GaAs semiconductor substrate, a n
−
collector layer on said n
+
subcollector layer, a p
+
base layer on said n
−
collector layer, a first non-doped spacer layer on said p
+
base layer, a n
+
&dgr;-doped layer on said first non-doped spacer layer, a second non-doped spacer layer on said n
+
&dgr;-doped layer, a n-type emitter layer on said second non-doped spacer layer, and a n
+
ohmic contact layer on said n-type emitter layer. Preferably, said n
+
subcollector layer is GaAs, and has a thickness of 0.2 to 1 &mgr;m, and a concentration of n=1×10
18
to 3×10
19
cm
−3
. Preferably, said n
−
collector layer is GaAs, and has a thickness of 0.2 to 1 &mgr;m, and a concentration of n
−
=1×10
16
to 1×10
17
cm
−3
. Preferably, said p
+
base layer is GaAs, and has a thickness of 0.05 to 0.2 &mgr;m, and a concentration of p=1×10
18
to 4×10
19
cm
−3
. Preferably, said first non-doped spacer is GaAs, and has a thickness of 10 to 200 Å. Preferably, said n
+
&dgr;-doped layer has a concentration of &dgr;(n
+
)=1×10
12
to 1&t

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